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/llvm-project/llvm/test/tools/llvm-mca/ARM/
H A Dm55-fp.s4 vabs.f16 s0, s2
5 vabs.f32 s0, s2
7 vadd.f16 s0, s2, s1
8 vadd.f32 s0, s2, s1
10 vcmp.f16 s1, s2
11 vcmp.f32 s1, s2
16 vcmpe.f16 s1, s2
17 vcmpe.f32 s1, s2
24 vcvt.f16.u16 s1, s2, #8
25 vcvt.f16.s16 s1, s2, #8
[all …]
H A Dm85-fp.s4 vabs.f16 s0, s2
5 vabs.f32 s0, s2
7 vadd.f16 s0, s2, s1
8 vadd.f32 s0, s2, s1
10 vcmp.f16 s1, s2
11 vcmp.f32 s1, s2
16 vcmpe.f16 s1, s2
17 vcmpe.f32 s1, s2
24 vcvt.f16.u16 s1, s2, #8
25 vcvt.f16.s16 s1, s2, #8
[all …]
H A Dm7-fp.s4 vabs.f32 s0, s2
6 vadd.f32 s0, s2, s1
8 vcmp.f32 s1, s2
12 vcvt.f32.u16 s1, s2, #8
13 vcvt.f32.s16 s1, s2, #8
14 vcvt.f32.u32 s1, s2, #8
15 vcvt.f32.s32 s1, s2, #8
16 vcvt.u16.f32 s1, s2, #8
17 vcvt.s16.f32 s1, s2, #8
18 vcvt.u32.f32 s1, s2, #8
[all …]
/llvm-project/llvm/test/MC/AMDGPU/
H A Dsopk.s17 s_movk_i32 s2, 0x6
18 // GCN: s_movk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb0]
20 s_cmovk_i32 s2, 0x6
21 // SICI: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]
22 // VI9: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb0]
23 // GFX10: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]
24 // GFX11: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]
26 s_cmpk_eq_i32 s2, 0x6
27 // SICI: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1]
28 // VI9: s_cmpk_eq_i32 s2,
[all...]
H A Dgfx1150_asm_salu_float.s687 s_add_f32 s5, s1, s2
690 s_add_f32 s105, s1, s2
693 s_add_f32 s5, s105, s2
696 s_add_f32 s5, s101, s2
699 s_add_f32 s5, vcc_lo, s2
702 s_add_f32 s5, vcc_hi, s2
705 s_add_f32 s5, m0, s2
708 s_add_f32 s5, exec_lo, s2
711 s_add_f32 s5, exec_hi, s2
714 s_add_f32 s5, 0, s2
[all …]
H A Dgfx7_asm_sopc.s3 s_cmp_eq_i32 s1, s2
6 s_cmp_eq_i32 s103, s2
9 s_cmp_eq_i32 flat_scratch_lo, s2
12 s_cmp_eq_i32 flat_scratch_hi, s2
15 s_cmp_eq_i32 vcc_lo, s2
18 s_cmp_eq_i32 vcc_hi, s2
21 s_cmp_eq_i32 tba_lo, s2
24 s_cmp_eq_i32 tba_hi, s2
27 s_cmp_eq_i32 tma_lo, s2
30 s_cmp_eq_i32 tma_hi, s2
[all …]
H A Dgfx12_asm_sopc.s3 s_cmp_lt_f32 s1, s2
6 s_cmp_lt_f32 s105, s2
9 s_cmp_lt_f32 s101, s2
12 s_cmp_lt_f32 vcc_lo, s2
15 s_cmp_lt_f32 vcc_hi, s2
18 s_cmp_lt_f32 m0, s2
21 s_cmp_lt_f32 exec_lo, s2
24 s_cmp_lt_f32 exec_hi, s2
27 s_cmp_lt_f32 0, s2
30 s_cmp_lt_f32 -1, s2
[all …]
H A Dgfx9_asm_sop2.s3 s_add_u32 s5, s1, s2
6 s_add_u32 s101, s1, s2
9 s_add_u32 flat_scratch_lo, s1, s2
12 s_add_u32 flat_scratch_hi, s1, s2
15 s_add_u32 vcc_lo, s1, s2
18 s_add_u32 vcc_hi, s1, s2
21 s_add_u32 ttmp15, s1, s2
24 s_add_u32 m0, s1, s2
27 s_add_u32 exec_lo, s1, s2
30 s_add_u32 exec_hi, s1, s2
[all …]
H A Dgfx8_asm_sopc.s3 s_cmp_eq_i32 s1, s2
6 s_cmp_eq_i32 s101, s2
9 s_cmp_eq_i32 flat_scratch_lo, s2
12 s_cmp_eq_i32 flat_scratch_hi, s2
15 s_cmp_eq_i32 vcc_lo, s2
18 s_cmp_eq_i32 vcc_hi, s2
21 s_cmp_eq_i32 tba_lo, s2
24 s_cmp_eq_i32 tba_hi, s2
27 s_cmp_eq_i32 tma_lo, s2
30 s_cmp_eq_i32 tma_hi, s2
[all …]
H A Dgfx7_asm_sop2.s3 s_add_u32 s5, s1, s2
6 s_add_u32 s103, s1, s2
9 s_add_u32 flat_scratch_lo, s1, s2
12 s_add_u32 flat_scratch_hi, s1, s2
15 s_add_u32 vcc_lo, s1, s2
18 s_add_u32 vcc_hi, s1, s2
21 s_add_u32 tba_lo, s1, s2
24 s_add_u32 tba_hi, s1, s2
27 s_add_u32 tma_lo, s1, s2
30 s_add_u32 tma_hi, s1, s2
[all …]
H A Dgfx8_asm_sop2.s3 s_add_u32 s5, s1, s2
6 s_add_u32 s101, s1, s2
9 s_add_u32 flat_scratch_lo, s1, s2
12 s_add_u32 flat_scratch_hi, s1, s2
15 s_add_u32 vcc_lo, s1, s2
18 s_add_u32 vcc_hi, s1, s2
21 s_add_u32 tba_lo, s1, s2
24 s_add_u32 tba_hi, s1, s2
27 s_add_u32 tma_lo, s1, s2
30 s_add_u32 tma_hi, s1, s2
[all …]
H A Dgfx9_asm_sopc.s3 s_cmp_eq_i32 s1, s2
6 s_cmp_eq_i32 s101, s2
9 s_cmp_eq_i32 flat_scratch_lo, s2
12 s_cmp_eq_i32 flat_scratch_hi, s2
15 s_cmp_eq_i32 vcc_lo, s2
18 s_cmp_eq_i32 vcc_hi, s2
21 s_cmp_eq_i32 ttmp15, s2
24 s_cmp_eq_i32 m0, s2
27 s_cmp_eq_i32 exec_lo, s2
30 s_cmp_eq_i32 exec_hi, s2
[all …]
H A Dsopk-err.s15 s_setreg_b32 0x1f803, s2
17 // GCN-NEXT: {{^}}s_setreg_b32 0x1f803, s2
20 s_setreg_b32 typo(0x40), s2
22 // GCN-NEXT: {{^}}s_setreg_b32 typo(0x40), s2
25 s_setreg_b32 hwreg(0x40), s2
27 // GCN-NEXT: {{^}}s_setreg_b32 hwreg(0x40), s2
30 s_setreg_b32 {id: 0x40}, s2
32 // GCN-NEXT: {{^}}s_setreg_b32 {id: 0x40}, s2
35 s_setreg_b32 hwreg(HW_REG_WRONG), s2
37 // GCN-NEXT: {{^}}s_setreg_b32 hwreg(HW_REG_WRONG), s2
[all …]
H A Dgfx12_asm_sop2.s237 s_add_f32 s5, s1, s2
240 s_add_f32 s105, s1, s2
243 s_add_f32 s5, s105, s2
246 s_add_f32 s5, s101, s2
249 s_add_f32 s5, vcc_lo, s2
252 s_add_f32 s5, vcc_hi, s2
255 s_add_f32 s5, m0, s2
258 s_add_f32 s5, exec_lo, s2
261 s_add_f32 s5, exec_hi, s2
264 s_add_f32 s5, 0, s2
[all …]
/llvm-project/libcxx/test/std/time/time.duration/time.duration.comparisons/
H A Dop_less.pass.cpp43 std::chrono::seconds s2(3); in main() local
44 assert(!(s1 < s2)); in main()
45 assert(!(s1 > s2)); in main()
46 assert( (s1 <= s2)); in main()
47 assert( (s1 >= s2)); in main()
51 std::chrono::seconds s2(4); in main() local
52 assert( (s1 < s2)); in main()
53 assert(!(s1 > s2)); in main()
54 assert( (s1 <= s2)); in main()
55 assert(!(s1 >= s2)); in main()
[all …]
H A Dop_equal.pass.cpp33 std::chrono::seconds s2(3); in main() local
34 assert(s1 == s2); in main()
35 assert(!(s1 != s2)); in main()
39 std::chrono::seconds s2(4); in main() local
40 assert(!(s1 == s2)); in main()
41 assert(s1 != s2); in main()
45 std::chrono::microseconds s2(3000); in main() local
46 assert(s1 == s2); in main()
47 assert(!(s1 != s2)); in main()
51 std::chrono::microseconds s2(4000); in main() local
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dscalar-float-sopc.ll10 ; SDAG-NEXT: s_cmp_lt_f32 s2, s3
12 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
14 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
20 ; GISEL-NEXT: s_cmp_lt_f32 s2, s3
22 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
24 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
25 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
38 ; SDAG-NEXT: s_cmp_eq_f32 s2, s3
40 ; SDAG-NEXT: s_cselect_b32 s2,
[all...]
H A Dcommute-compares-scalar-float.ll8 ; SDAG-NEXT: s_cmp_gt_f32 s2, 2.0
10 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
12 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
18 ; GISEL-NEXT: s_cmp_gt_f32 s2, 2.0
20 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
22 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
23 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
36 ; SDAG-NEXT: s_cmp_lt_f32 s2, 2.0
38 ; SDAG-NEXT: s_cselect_b32 s2,
[all...]
H A Dudivrem.ll42 ; GFX6-NEXT: s_mov_b32 s2, -1
43 ; GFX6-NEXT: s_mov_b32 s6, s2
94 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
171 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
172 ; GFX6-NEXT: s_sub_i32 s6, 0, s2
185 ; GFX6-NEXT: s_mul_i32 s6, s6, s2
187 ; GFX6-NEXT: s_sub_i32 s6, s0, s2
188 ; GFX6-NEXT: s_cmp_ge_u32 s0, s2
190 ; GFX6-NEXT: s_sub_i32 s6, s0, s2
191 ; GFX6-NEXT: s_cmp_ge_u32 s0, s2
[all...]
/llvm-project/llvm/test/CodeGen/Hexagon/intrinsics/
H A Dxtype_shift.ll8 declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32)
10 %z = call i64 @llvm.hexagon.S2.asr.i.p(i64 %a, i32 0)
15 declare i64 @llvm.hexagon.S2.lsr.i.p(i64, i32)
17 %z = call i64 @llvm.hexagon.S2.lsr.i.p(i64 %a, i32 0)
22 declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32)
24 %z = call i64 @llvm.hexagon.S2.asl.i.p(i64 %a, i32 0)
29 declare i32 @llvm.hexagon.S2.asr.i.r(i32, i32)
31 %z = call i32 @llvm.hexagon.S2.asr.i.r(i32 %a, i32 0)
36 declare i32 @llvm.hexagon.S2.lsr.i.r(i32, i32)
38 %z = call i32 @llvm.hexagon.S2
[all...]
H A Dxtype_perm.ll52 declare i32 @llvm.hexagon.S2.vrndpackwh(i64)
54 %z = call i32 @llvm.hexagon.S2.vrndpackwh(i64 %a)
59 declare i32 @llvm.hexagon.S2.vrndpackwhs(i64)
61 %z = call i32 @llvm.hexagon.S2.vrndpackwhs(i64 %a)
67 declare i32 @llvm.hexagon.S2.vsathub(i64)
69 %z = call i32 @llvm.hexagon.S2.vsathub(i64 %a)
74 declare i32 @llvm.hexagon.S2.vsatwh(i64)
76 %z = call i32 @llvm.hexagon.S2.vsatwh(i64 %a)
81 declare i32 @llvm.hexagon.S2.vsatwuh(i64)
83 %z = call i32 @llvm.hexagon.S2
[all...]
H A Dxtype_bit.ll8 declare i32 @llvm.hexagon.S2.clbp(i64)
10 %z = call i32 @llvm.hexagon.S2.clbp(i64 %a)
15 declare i32 @llvm.hexagon.S2.cl0p(i64)
17 %z = call i32 @llvm.hexagon.S2.cl0p(i64 %a)
22 declare i32 @llvm.hexagon.S2.cl1p(i64)
24 %z = call i32 @llvm.hexagon.S2.cl1p(i64 %a)
50 declare i32 @llvm.hexagon.S2.cl0(i32)
52 %z = call i32 @llvm.hexagon.S2.cl0(i32 %a)
57 declare i32 @llvm.hexagon.S2.cl1(i32)
59 %z = call i32 @llvm.hexagon.S2
[all...]
/llvm-project/llvm/test/CodeGen/Thumb2/
H A Dmve-vecreduce-fminmax.ll18 ; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3
20 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2
26 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2
39 ; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3
41 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2
49 ; CHECK-NOFP-NEXT: vminnm.f32 s2, s2, s6
50 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2
[all...]
/llvm-project/llvm/test/CodeGen/ARM/
H A Dfp16-vminmaxnm-safe.ll9 ; CHECK-NEXT: vmov.f16 s2, r1
10 ; CHECK-NEXT: vcmp.f16 s2, s0
12 ; CHECK-NEXT: vselgt.f16 s0, s0, s2
25 ; CHECK-NEXT: vmov.f16 s2, r0
26 ; CHECK-NEXT: vcmp.f16 s2, s0
28 ; CHECK-NEXT: vselgt.f16 s0, s2, s0
41 ; CHECK-NEXT: vmov.f16 s2, r0
42 ; CHECK-NEXT: vcmp.f16 s2, s0
44 ; CHECK-NEXT: vselge.f16 s0, s0, s2
57 ; CHECK-NEXT: vmov.f16 s2, r
[all...]
/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx1150_dasm_salu_float.txt687 # GFX1150: s_add_f32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0xa0]
690 # GFX1150: s_add_f32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0xa0]
693 # GFX1150: s_add_f32 s5, s105, s2 ; encoding: [0x69,0x02,0x05,0xa0]
696 # GFX1150: s_add_f32 s5, s101, s2 ; encoding: [0x65,0x02,0x05,0xa0]
699 # GFX1150: s_add_f32 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x05,0xa0]
702 # GFX1150: s_add_f32 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x05,0xa0]
705 # GFX1150: s_add_f32 s5, m0, s2 ; encoding: [0x7d,0x02,0x05,0xa0]
708 # GFX1150: s_add_f32 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x05,0xa0]
711 # GFX1150: s_add_f32 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x05,0xa0]
714 # GFX1150: s_add_f32 s5, 0, s2 ; encoding: [0x80,0x02,0x05,0xa0]
[all …]

12345678910>>...141