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/llvm-project/llvm/test/CodeGen/VE/Scalar/
H A Dsymbol_relocation_tls.ll22 ; GENDYN-NEXT: lea %s12, (8)
24 ; GENDYN-NEXT: and %s12, %s12, (32)0
25 ; GENDYN-NEXT: lea.sl %s12, (%s10, %s12)
27 ; GENDYN-NEXT: bsic %s10, (, %s12)
42 ; GENDYNPIC-NEXT: lea %s12, (8)
44 ; GENDYNPIC-NEXT: and %s12, %s12, (32)0
45 ; GENDYNPIC-NEXT: lea.sl %s12, (%s10, %s12)
47 ; GENDYNPIC-NEXT: bsic %s10, (, %s12)
61 ; GENDYN-NEXT: lea %s12, (8)
63 ; GENDYN-NEXT: and %s12, %s12, (32)0
[all …]
H A Dtls.ll19 ; GENDYN-NEXT: lea %s12, __tls_get_addr@plt_lo(8)
20 ; GENDYN-NEXT: and %s12, %s12, (32)0
21 ; GENDYN-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
22 ; GENDYN-NEXT: bsic %s10, (, %s12)
35 ; GENDYNPIC-NEXT: lea %s12, __tls_get_addr@plt_lo(8)
36 ; GENDYNPIC-NEXT: and %s12, %s12, (32)0
37 ; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
38 ; GENDYNPIC-NEXT: bsic %s10, (, %s12)
60 ; GENDYN-NEXT: lea %s12, __tls_get_addr@plt_lo(8)
61 ; GENDYN-NEXT: and %s12, %s12, (32)0
[all …]
H A Dstackframe_call.ll35 ; CHECK-NEXT: lea.sl %s12, fun@hi(, %s2)
36 ; CHECK-NEXT: bsic %s10, (, %s12)
65 ; PIC-NEXT: lea %s12, fun@plt_lo(-24)
66 ; PIC-NEXT: and %s12, %s12, (32)0
68 ; PIC-NEXT: lea.sl %s12, fun@plt_hi(%s16, %s12)
69 ; PIC-NEXT: bsic %s10, (, %s12)
104 ; CHECK-NEXT: lea.sl %s12, fun@hi(, %s0)
106 ; CHECK-NEXT: bsic %s10, (, %s12)
136 ; PIC-NEXT: lea %s12, fun@plt_lo(-24)
137 ; PIC-NEXT: and %s12, %s12, (32)0
[all …]
H A Dfp_frem.ll40 ; CHECK-NEXT: lea.sl %s12, fmodf@hi(, %s2)
41 ; CHECK-NEXT: bsic %s10, (, %s12)
53 ; CHECK-NEXT: lea.sl %s12, fmod@hi(, %s2)
54 ; CHECK-NEXT: bsic %s10, (, %s12)
66 ; CHECK-NEXT: lea.sl %s12, fmodl@hi(, %s4)
67 ; CHECK-NEXT: bsic %s10, (, %s12)
80 ; CHECK-NEXT: lea.sl %s12, fmodf@hi(, %s0)
82 ; CHECK-NEXT: bsic %s10, (, %s12)
95 ; CHECK-NEXT: lea.sl %s12, fmod@hi(, %s0)
97 ; CHECK-NEXT: bsic %s10, (, %s12)
[all …]
H A Dbuiltin_sjlj_landingpad.ll58 ; CHECK-NEXT: lea.sl %s12, _Unwind_SjLj_Register@hi(, %s0)
60 ; CHECK-NEXT: bsic %s10, (, %s12)
66 ; CHECK-NEXT: lea.sl %s12, errorbar@hi(, %s0)
67 ; CHECK-NEXT: bsic %s10, (, %s12)
72 ; CHECK-NEXT: lea.sl %s12, _Unwind_SjLj_Unregister@hi(, %s0)
74 ; CHECK-NEXT: bsic %s10, (, %s12)
118 ; CHECK-NEXT: lea.sl %s12, _Unwind_SjLj_Unregister@hi(, %s0)
120 ; CHECK-NEXT: bsic %s10, (, %s12)
178 ; PIC-NEXT: lea %s12, _Unwind_SjLj_Register@plt_lo(-24)
179 ; PIC-NEXT: and %s12,
[all...]
H A Dpic_access_static_data.ll49 ; CHECK-NEXT: lea %s12, func@plt_lo(-24)
50 ; CHECK-NEXT: and %s12, %s12, (32)0
52 ; CHECK-NEXT: lea.sl %s12, func@plt_hi(%s16, %s12)
53 ; CHECK-NEXT: bsic %s10, (, %s12)
62 ; CHECK-NEXT: lea %s12, printf@plt_lo(-24)
63 ; CHECK-NEXT: and %s12, %s12, (32)0
65 ; CHECK-NEXT: lea.sl %s12, printf@plt_hi(%s16, %s12)
67 ; CHECK-NEXT: bsic %s10, (, %s12)
H A Dpow.ll33 ; CHECK-NEXT: lea.sl %s12, powf@hi(, %s2)
34 ; CHECK-NEXT: bsic %s10, (, %s12)
49 ; CHECK-NEXT: lea.sl %s12, pow@hi(, %s2)
50 ; CHECK-NEXT: bsic %s10, (, %s12)
65 ; CHECK-NEXT: lea.sl %s12, powl@hi(, %s4)
66 ; CHECK-NEXT: bsic %s10, (, %s12)
113 ; CHECK-NEXT: lea.sl %s12, powf@hi(, %s0)
115 ; CHECK-NEXT: bsic %s10, (, %s12)
128 ; CHECK-NEXT: lea.sl %s12, pow@hi(, %s0)
130 ; CHECK-NEXT: bsic %s10, (, %s12)
[all …]
H A Dfma.ll40 ; CHECK-NEXT: lea.sl %s12, fmaf@hi(, %s3)
41 ; CHECK-NEXT: bsic %s10, (, %s12)
56 ; CHECK-NEXT: lea.sl %s12, fma@hi(, %s3)
57 ; CHECK-NEXT: bsic %s10, (, %s12)
72 ; CHECK-NEXT: lea.sl %s12, fmal@hi(, %s6)
73 ; CHECK-NEXT: bsic %s10, (, %s12)
145 ; CHECK-NEXT: lea.sl %s12, fmaf@hi(, %s1)
147 ; CHECK-NEXT: bsic %s10, (, %s12)
160 ; CHECK-NEXT: lea.sl %s12, fma@hi(, %s1)
162 ; CHECK-NEXT: bsic %s10, (, %s12)
[all …]
/llvm-project/llvm/test/MC/VE/
H A DCMOV.s6 # CHECK-INST: cmov.l.at %s11, %s12, 63
8 cmov.l %s11, %s12, 63
10 # CHECK-INST: cmov.w.at %s11, %s12, %s13
12 cmov.w.at %s11, %s12, %s13
14 # CHECK-INST: cmov.d.af %s11, (20)0, %s12
16 cmov.d.af %s11, (20)0, %s12
18 # CHECK-INST: cmov.s.gt %s11, (63)1, %s12
20 cmov.s.gt %s11, (63)1, %s12
22 # CHECK-INST: cmov.l.lt %s11, %s12, 63
24 cmov.l.lt %s11, %s12, 63
[all …]
H A DVST.s6 # CHECK-INST: vst %v11, 23, %s12
8 vst %v11, 23, %s12
18 # CHECK-INST: vst.nc.ot %v12, %s12, 0
20 vst.nc.ot %v12, %s12, 0
22 # CHECK-INST: vst %v11, 23, %s12
24 vst %v11, 23, %s12, %vm0
34 # CHECK-INST: vst.nc.ot %v12, %s12, 0, %vm8
36 vst.nc.ot %v12, %s12, 0, %vm8
38 # CHECK-INST: vstu %v11, 23, %s12
40 vstu %v11, 23, %s12
[all …]
H A DVGT.s6 # CHECK-INST: vgt %v11, %v13, 23, %s12
8 vgt %v11, %v13, 23, %s12
10 # CHECK-INST: vgt.nc %vix, %s12, 63, 0
12 vgt.nc %vix, %s12, 63, 0
18 # CHECK-INST: vgt.nc %v12, %v63, %s12, 0, %vm3
20 vgt.nc %v12, %v63, %s12, 0, %vm3
22 # CHECK-INST: vgtu %v11, %v13, 23, %s12
24 vgtu %v11, %v13, 23, %s12
26 # CHECK-INST: vgtu.nc %vix, %s12, 63, 0
28 vgtu.nc %vix, %s12, 63, 0
[all …]
H A DVSC.s6 # CHECK-INST: vsc %v11, %v13, 23, %s12
8 vsc %v11, %v13, 23, %s12
10 # CHECK-INST: vsc.nc %vix, %s12, 63, 0
12 vsc.nc %vix, %s12, 63, 0
18 # CHECK-INST: vsc.nc.ot %v12, %v63, %s12, 0, %vm3
20 vsc.nc.ot %v12, %v63, %s12, 0, %vm3
22 # CHECK-INST: vscu %v11, %v13, 23, %s12
24 vscu %v11, %v13, 23, %s12
26 # CHECK-INST: vscu.nc %vix, %s12, 63, 0
28 vscu.nc %vix, %s12, 63, 0
[all …]
H A Dsym-tls.s8 lea %s12, __tls_get_addr@plt_lo(8)
9 and %s12, %s12, (32)0
10 lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
11 bsic %s10, (, %s12)
16 # CHECK-NEXT: lea %s12, __tls_get_addr@plt_lo(8)
17 # CHECK-NEXT: and %s12, %s12, (32)0
18 # CHECK-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
19 # CHECK-NEXT: bsic %s10, (, %s12)
H A DVLD.s6 # CHECK-INST: vld %v11, 23, %s12
8 vld %v11, 23, %s12
18 # CHECK-INST: vldu.nc %v12, %s12, 0
20 vldu.nc %v12, %s12, 0
22 # CHECK-INST: vldl.sx %v11, 23, %s12
24 vldl.sx %v11, 23, %s12
34 # CHECK-INST: vldl.zx.nc %v12, %s12, %s63
36 vldl.zx.nc %v12, %s12, %s63
38 # CHECK-INST: vld2d %v11, 23, %s12
40 vld2d %v11, 23, %s12
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dret-vec-promote.ll25 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
27 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
28 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s12)
41 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
43 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
44 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s12>) = G_IMPLICIT_DEF
47 …; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s12), [[C]]…
48 …; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s12>) = G_INSERT_VECTOR_ELT [[IVEC]], [[TRUNC1]](s12), [[…
49 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[IVEC1]](<2 x s12>)
63 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Damdgpu-nsa-threshold.ll12 ; ATTRIB-NEXT: s_mov_b32 s12, exec_lo
15 ; ATTRIB-NEXT: s_and_b32 exec_lo, exec_lo, s12
22 ; FORCE-2-NEXT: s_mov_b32 s12, exec_lo
25 ; FORCE-2-NEXT: s_and_b32 exec_lo, exec_lo, s12
32 ; FORCE-3-NEXT: s_mov_b32 s12, exec_lo
35 ; FORCE-3-NEXT: s_and_b32 exec_lo, exec_lo, s12
42 ; FORCE-4-NEXT: s_mov_b32 s12, exec_lo
45 ; FORCE-4-NEXT: s_and_b32 exec_lo, exec_lo, s12
57 ; ATTRIB-NEXT: s_mov_b32 s12, exec_lo
60 ; ATTRIB-NEXT: s_and_b32 exec_lo, exec_lo, s12
[all …]
H A Dllvm.amdgcn.image.sample.a16.dim.ll19 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
21 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
28 ; GFX11-NEXT: s_mov_b32 s12, exec_lo
30 ; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12
37 ; GFX12-NEXT: s_mov_b32 s12, exec_lo
39 ; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
62 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
65 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
72 ; GFX11-NEXT: s_mov_b32 s12, exec_lo
75 ; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12
[all...]
H A Dllvm.amdgcn.image.gather4.a16.dim.ll21 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
24 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
31 ; GFX12-NEXT: s_mov_b32 s12, exec_lo
34 ; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
57 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
60 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
67 ; GFX12-NEXT: s_mov_b32 s12, exec_lo
70 ; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12
93 ; GFX10-NEXT: s_mov_b32 s12, exec_lo
96 ; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12
[all...]
/llvm-project/llvm/test/CodeGen/VE/Vector/
H A Dfastcc_caller.ll17 ; CHECK-NEXT: lea.sl %s12, sample_add@hi(, %s0)
20 ; CHECK-NEXT: bsic %s10, (, %s12)
34 ; CHECK-NEXT: lea.sl %s12, stack_callee_int@hi(, %s0)
44 ; CHECK-NEXT: bsic %s10, (, %s12)
58 ; CHECK-NEXT: lea.sl %s12, stack_callee_int_szext@hi(, %s0)
68 ; CHECK-NEXT: bsic %s10, (, %s12)
82 ; CHECK-NEXT: lea.sl %s12, stack_callee_float@hi(, %s0)
92 ; CHECK-NEXT: bsic %s10, (, %s12)
104 ; CHECK-NEXT: lea.sl %s12, stack_callee_float@hi(, %s1)
113 ; CHECK-NEXT: bsic %s10, (, %s12)
[all …]
/llvm-project/compiler-rt/test/asan/TestCases/Linux/
H A Dsized_delete_test.cpp17 struct S12 { struct
35 void Del12(S12 *x) { in Del12() argument
39 void Del12NoThrow(S12 *x) { in Del12NoThrow()
43 void Del12Ar(S12 *x) { in Del12Ar()
47 void Del12ArNoThrow(S12 *x) { in Del12ArNoThrow()
56 Del12(new S12); in main()
57 Del12NoThrow(new S12); in main()
58 Del12Ar(new S12[100]); in main()
59 Del12ArNoThrow(new S12[100]); in main()
63 Del12Ar(reinterpret_cast<S12*>(new S20[100])); in main()
[all …]
/llvm-project/llvm/test/MC/ARM/
H A Dvpush-vpop.s7 vpush {s8, s9, s10, s11, s12}
9 vpop {s8, s9, s10, s11, s12}
12 vpush.16 {s8, s9, s10, s11, s12}
14 vpop.64 {s8, s9, s10, s11, s12}
17 @ CHECK-THUMB: vpush {s8, s9, s10, s11, s12} @ encoding: [0x2d,0xed,0x05,0x4a]
19 @ CHECK-THUMB: vpop {s8, s9, s10, s11, s12} @ encoding: [0xbd,0xec,0x05,0x4a]
22 @ CHECK-ARM: vpush {s8, s9, s10, s11, s12} @ encoding: [0x05,0x4a,0x2d,0xed]
24 @ CHECK-ARM: vpop {s8, s9, s10, s11, s12} @ encoding: [0x05,0x4a,0xbd,0xec]
27 @ CHECK-THUMB: vpush {s8, s9, s10, s11, s12} @ encoding: [0x2d,0xed,0x05,0x4a]
29 @ CHECK-THUMB: vpop {s8, s9, s10, s11, s12} @ encoding: [0xbd,0xec,0x05,0x4a]
[all …]
H A Dfullfp16.s98 vcvt.u32.f16 s12, s12, #20
106 @ ARM: vcvt.u32.f16 s12, s12, #20 @ encoding: [0xc6,0x69,0xbf,0xee]
114 @ THUMB: vcvt.u32.f16 s12, s12, #20 @ encoding: [0xbf,0xee,0xc6,0x69]
167 vmaxnm.f16 s5, s12, s0
168 @ ARM: vmaxnm.f16 s5, s12, s0 @ encoding: [0x00,0x29,0xc6,0xfe]
169 @ THUMB: vmaxnm.f16 s5, s12, s0 @ encoding: [0xc6,0xfe,0x00,0x29]
171 vminnm.f16 s0, s0, s12
172 @ ARM: vminnm.f16 s0, s0, s12 @ encoding: [0x46,0x09,0x80,0xfe]
173 @ THUMB: vminnm.f16 s0, s0, s12 @ encoding: [0x80,0xfe,0x46,0x09]
196 vrinta.f16 s12, s1
[all …]
H A Dfullfp16-neg.s70 vcvt.u32.f16 s12, s12, #20
119 vmaxnm.f16 s5, s12, s0
122 vminnm.f16 s0, s0, s12
140 vrinta.f16 s12, s1
141 vrinta.f16.f16 s12, s1
145 vrintn.f16 s12, s1
146 vrintn.f16.f16 s12, s1
150 vrintp.f16 s12, s1
151 vrintp.f16.f16 s12, s1
155 vrintm.f16 s12, s1
[all …]
/llvm-project/llvm/test/CodeGen/Thumb2/
H A Dmve-fmas.ll21 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
24 ; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
25 ; CHECK-MVE-NEXT: vmovx.f16 s12, s1
28 ; CHECK-MVE-NEXT: vmla.f16 s12, s8, s4
30 ; CHECK-MVE-NEXT: vins.f16 s1, s12
31 ; CHECK-MVE-NEXT: vmovx.f16 s12, s2
34 ; CHECK-MVE-NEXT: vmla.f16 s12, s8, s4
42 ; CHECK-MVE-NEXT: vins.f16 s2, s12
66 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
69 ; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
[all...]
/llvm-project/llvm/test/CodeGen/ARM/
H A Dfp16-insert-extract.ll175 ; CHECKHARD-NEXT: vmovx.f16 s12, s1
176 ; CHECKHARD-NEXT: vmov r0, s12
179 ; CHECKHARD-NEXT: vmovx.f16 s12, s4
188 ; CHECKHARD-NEXT: vmov r0, s12
189 ; CHECKHARD-NEXT: vmovx.f16 s12, s0
190 ; CHECKHARD-NEXT: vmov r1, s12
191 ; CHECKHARD-NEXT: vmovx.f16 s12, s3
196 ; CHECKHARD-NEXT: vmov r0, s12
198 ; CHECKHARD-NEXT: vmov r1, s12
199 ; CHECKHARD-NEXT: vmovx.f16 s12, s9
[all …]

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