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/freebsd-src/sys/contrib/alpine-hal/
H A Dal_hal_udma_regs_gen.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
112 /* [0x0] TX queue 0/1 Target-Address */
114 /* [0x4] TX queue 2/3 Target-Address */
116 /* [0x8] RX queue 0/1 Target-Address */
118 /* [0xc] RX queue 2/3 Target-Address */
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/freebsd-src/share/man/man4/
H A Dena.41 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
56 through an Admin Queue
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H A Dgve.41 .\" SPDX-License-Identifier: BSD-3-Clause
3 .\" Copyright (c) 2023-2024 Google LLC
39 .Bd -ragged -offset indent
46 .Bd -literal -offset indent
51 It is required to support per-V
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H A Diflib.428 .Bl -tag -width indent
30 Override the number of RX descriptors for each queue.
37 Override the number of TX descriptors for each queue.
45 If not set, the lower of the number of TX or RX queues will be used for both.
47 Set the number of RX queues.
48 If zero, the number of RX queues is derived from the number of cores on the
56 Disables MSI-X interrupts for the device.
62 Requests that RX and TX queues not be paired on the same core.
63 If this is zero or not set, an RX and TX queue pair will be assigned to each
65 When set to a non-zero value, TX queues are assigned to cores following the
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/freebsd-src/sys/dev/vge/
H A Dif_vgereg.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
54 #define VGE_RXCTL 0x06 /* RX control register */
82 #define VGE_RXHOSTERR 0x23 /* RX host error status */
86 #define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */
87 #define VGE_RXQCSRS 0x32 /* RX queue ctl/status set */
88 #define VGE_TXQCSRC 0x34 /* TX queue ctl/status clear */
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/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dintel,ixp4xx-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Linus Walleij <linus.walleij@linaro.org>
18 Processing Engine) and the IXP4xx Queue Manager to process
24 const: intel,ixp4xx-ethernet
30 queue-rx:
31 $ref: /schemas/types.yaml#/definitions/phandle-array
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H A Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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H A Dintel,ixp4xx-hss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
15 Processing Engine) and the IXP4xx Queue Manager to process
20 const: intel,ixp4xx-hss
26 intel,npe-handle:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
30 - description: phandle to the NPE this HSS instance is using
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H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jos
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/freebsd-src/sys/dev/bxe/
H A Decore_mfw_req.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
115 uint32_t promiscuous_mode; /* Promiscuous Mode. non-zero true */
116 uint32_t txq_size; /* TX Descriptors Queue Size */
117 uint32_t rxq_size; /* RX Descriptors Queue Size */
118 /* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
120 /* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */
135 /* QoS Priority (per 802.1p). 0-7255 */
137 uint32_t txq_size; /* FCoE TX Descriptors Queue Size. */
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/freebsd-src/sys/dev/ice/
H A Dice_iflib_txrx.c1 /* SPDX-License-Identifier: BSD-3-Clause */
34 * @brief iflib Tx/Rx hotpath
36 * Main location for the iflib Tx/Rx hotpath implementation.
44 /* Tx/Rx hotpath utility functions */
78 /* Macro to help extract the NIC mode flexible Rx descriptor fields from the
79 * advanced 32byte Rx descriptors.
82 (((struct ice_32b_rx_flex_desc_nic *)desc)->field)
86 * @brief Tx/Rx operations for the iflib stack
88 * Structure defining the Tx and Rx related operations that iflib can request
105 * @brief Tx/Rx operations for the iflib stack, for subinterfaces
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H A Dice_iflib.h1 /* SPDX-License-Identifier: BSD-3-Clause */
37 * implementation, including the Tx and Rx queue structures and the ice_softc
65 * ASSERT_CTX_LOCKED - Assert that the iflib context lock is held
71 #define ASSERT_CTX_LOCKED(sc) sx_assert((sc)->iflib_ctx_lock, SA_XLOCKED)
74 * IFLIB_CTX_LOCK - lock the iflib context lock
79 #define IFLIB_CTX_LOCK(sc) sx_xlock((sc)->iflib_ctx_loc
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/freebsd-src/sys/contrib/device-tree/Bindings/crypto/
H A Dintel,ixp4xx-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
21 const: intel,ixp4xx-crypto
23 intel,npe-handle:
24 $ref: /schemas/types.yaml#/definitions/phandle-array
26 - items:
27 - description: phandle to the NPE this crypto engine
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/freebsd-src/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2e-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cell
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H A Dkeystone-k2l-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cell
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H A Dkeystone-k2hk-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cell
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H A Dkeystone-k2g-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,66ak2g-navss-qm";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
13 power-domain
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/freebsd-src/sys/contrib/dev/iwlwifi/
H A Diwl-op-mode.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2021, 2024 Intel Corporation
4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
12 #include "iwl-dbg-tl
95 void (*rx)(struct iwl_op_mode *op_mode, struct napi_struct *napi, global() member
145 iwl_op_mode_rx_rss(struct iwl_op_mode * op_mode,struct napi_struct * napi,struct iwl_rx_cmd_buffer * rxb,unsigned int queue) iwl_op_mode_rx_rss() argument
158 iwl_op_mode_queue_full(struct iwl_op_mode * op_mode,int queue) iwl_op_mode_queue_full() argument
164 iwl_op_mode_queue_not_full(struct iwl_op_mode * op_mode,int queue) iwl_op_mode_queue_not_full() argument
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/freebsd-src/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
174 /** Tx to Rx switching decision type */
182 /** Tx to Rx VLAN ID selection type */
192 /** Rx descriptor configurations */
193 /* Note: when selecting rx descriptor field to inner packet, then that field
194 * will be set according to inner packet when packet is tunneled, for non-tunneled
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/freebsd-src/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_port.h2 * Copyright 2008-2013 Freescale Semiconductor Inc.
150 /** @Description BMI Rx port register map */
152 uint32_t fmbm_rcfg; /**< Rx Configuration */
153 uint32_t fmbm_rst; /**< Rx Status */
154 uint32_t fmbm_rda; /**< Rx DMA attributes*/
155 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
156 uint32_t fmbm_rfed; /**< Rx Frame End Data*/
157 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
158 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
159 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
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/freebsd-src/sys/dev/e1000/
H A De1000_defines.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
132 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
199 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
206 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
207 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
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/freebsd-src/sys/contrib/dev/iwlwifi/pcie/
H A Drx.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2003-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 #include "iwl-prp
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H A Dinternal.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2003-2015, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
18 #include "iwl-f
74 u32 rx; global() member
164 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; global() member
456 iwl_pcie_clear_irq(struct iwl_trans * trans,int queue) iwl_pcie_clear_irq() argument
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/freebsd-src/sys/arm/ti/cpsw/
H A Dif_cpsw.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
39 * a 3-port store-and-forward switch connected to two independent
252 { -1, 0 }
331 if ((_sc)->debu
385 cpsw_write_hdp_slot(sc,queue,slot) global() argument
388 cpsw_read_cp(sc,queue) global() argument
390 cpsw_write_cp(sc,queue,val) global() argument
392 cpsw_write_cp_slot(sc,queue,slot) global() argument
499 cpsw_add_slots(struct cpsw_softc * sc,struct cpsw_queue * queue,int requested) cpsw_add_slots() argument
2674 cpsw_add_queue_sysctls(struct sysctl_ctx_list * ctx,struct sysctl_oid * node,struct cpsw_queue * queue) cpsw_add_queue_sysctls() argument
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/freebsd-src/sys/dev/qlnx/qlnxe/
H A Decore_l2_api.h2 * Copyright (c) 2017-2018 Cavium, Inc.
107 /* Indirection table consist of rx queue handles */
204 /* Add / remove / move / remove-all unicast MAC-VLAN filters.
236 * @brief ecore_eth_rx_queue_start - RX Queue Start Ramrod
238 * This ramrod initializes an RX Queue for a VPort. An Assert is generated if
263 * @brief ecore_eth_rx_queue_stop - This ramrod closes an Rx queue
266 * @param p_rxq Handler of queue to close
283 * @brief - TX Queue Start Ramrod
285 * This ramrod initializes a TX Queue for a VPort. An Assert is generated if
308 * @brief ecore_eth_tx_queue_stop - closes a Tx queue
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