Lines Matching +full:queue +full:- +full:rx
1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
174 /** Tx to Rx switching decision type */
182 /** Tx to Rx VLAN ID selection type */
192 /** Rx descriptor configurations */
193 /* Note: when selecting rx descriptor field to inner packet, then that field
194 * will be set according to inner packet when packet is tunneled, for non-tunneled
257 /** Ethernet Rx completion descriptor */
280 * received with priority 7, also, when RX queues
285 * 1) if specific a queue is not used, the caller must
286 * make set the prio_q_map to 0 otherwise that queue
327 uint8_t l4_header_len; /**< in words(32-bits) */
339 /* Packet Rx flags when adding buffer to receive queue */
342 * Target-ID to be assigned to the packet descriptors
343 * Requires Target-ID in descriptor to be enabled for the specific UDMA
344 * queue.
351 /* Packet Rx flags set by HW when receiving packet */
356 /* Packet Rx flags - word 3 in Rx completion descriptor */
371 uint32_t flags; /**< see flags above, depends on context(tx or rx) */
386 * Target-ID to be assigned to the packet descriptors
387 * Requires Target-ID in descriptor to be enabled for the specific UDMA
388 * queue.
392 uint32_t rx_header_len; /**< header buffer length of rx packet, not used */
429 uint8_t enable_rx_parser; /**< config and enable rx parsing */
448 uint8_t enable_rx_parser; /**< when true, the rx epe parser will be enabled */
464 * - initialize the adapter data structure
465 * - initialize the Tx and Rx UDMA
466 * - enable the Tx and Rx UDMA, the rings will be still disabled at this point.
507 * Configure and enable a queue ring
510 * @param type tx or rx
511 * @param qid queue index
512 * @param q_params queue parameters
521 * enable a queue if it was previously disabled
524 * @param type tx or rx
525 * @param qid queue index
527 * @return -EPERM (not implemented yet).
532 * disable a queue
534 * @param type tx or rx
535 * @param qid queue index
537 * @return -EPERM (not implemented yet).
555 * stop the mac tx and rx paths.
563 * start the mac tx and rx paths.
571 * Perform gearbox reset for tx lanes And/Or Rx lanes.
577 * @param tx_reset assert and de-assert reset for tx lanes
578 * @param rx_reset assert and de-assert reset for rx lanes
647 * configure minimum and maximum rx packet length
650 * @param min_rx_len minimum rx packet length
651 * @param max_rx_len maximum rx packet length
721 * @param qid queue index
730 al_udma_q_handle_get(&adapter->tx_udma, qid, &udma_q); in al_eth_tx_available_get()
736 * prepare packet descriptors in tx queue.
742 * @param tx_dma_q pointer to UDMA tx queue
754 * @param tx_dma_q pointer to UDMA tx queue
766 * @param tx_dma_q pointer to UDMA tx queue
785 /* RX */
787 * Config the RX descriptor fields
810 * Configure RX header split
827 * enable / disable header split in the udma queue.
828 * length will be taken from the udma configuration to enable different length per queue.
832 * @param qid the queue id to enable/disable header split
843 * add buffer to receive queue
845 * @param rx_dma_q pointer to UDMA rx queue
858 * notify the hw engine about rx descriptors that were added to the receive queue
860 * @param rx_dma_q pointer to UDMA rx queue
861 * @param descs_num number of rx descriptors
867 * get packet from RX completion ring
869 * @param rx_dma_q pointer to UDMA rx queue
875 * were those buffers inserted into the ring of the receive queue.
883 /* RX parser table */
895 * update rx parser entry
909 …th_thash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma, uint32_t queue);
918 * bits[1:0] - input selection: selects the input for the thash (2/4 tuple, inner/outer)
919 * bit[2] - selects whether to use thash output, or default values for the queue and udma
921 * bits[9:5] defualt queue: the queue index to select when bit 2 above was unset
1011 /** where to select the initial queue from */
1025 /** target queue will be built up from the priority and initial queue */
1027 AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO_TABLE = 0, /**< target queue is the output of priority table */
1028 AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO = 1, /**< target queue is the priority */
1029 AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO_QUEUE = 2, /**< target queue is initial queue[0], priority[1] */
1030 AL_ETH_CTRL_TABLE_QUEUE_SEL_2_NO_PRIO = 3, /**< target queue is the initial */
1064 enum AL_ETH_CTRL_TABLE_QUEUE_SEL_1 queue_sel_1; /**< queue id source */
1065 enum AL_ETH_CTRL_TABLE_QUEUE_SEL_2 queue_sel_2; /**< mix queue id with priority */
1120 uint8_t qid; /**< target queue */
1160 * The HW uses this table to translate between priority to queue index.
1165 * @param qid the queue index to set for this entry (priority).
1178 * @param prio the queue index to set for this entry (priority).
1191 * @param prio the queue index to set for this entry (priority).
1204 * @param qid the target queue index to set for this entry.
1262 * Configure default queue register
1263 * When the control table entry queue selection 1 set to AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG<n>,
1264 * then the target queue will be set according to the register n of the default
1265 * queue registers.
1278 * When the control table entry queue selection 1 set to AL_ETH_CTRL_TABLE_PRIO_SEL_1_REG<n>,
1326 uint8_t qid; /**< target queue id */
1347 * to a specific UDMA/queue. The override filters apply only for
1397 * This is a generic time-stamp mechanism that can be used as generic to
1398 * time-stamp every received or transmit packet it can also support IEEE 1588v2
1400 * In addition to time-stamp, an internal system time is maintained. For
1403 * to the rest of the ports - that is outside the scope of the Ethernet
1404 * Controller - please refer to Annapurna Labs Alpine Hardware Wiki
1411 * Rx timestamps requires using 8 words (8x4 bytes) rx completion descriptor
1424 * This is the size of the on-chip array that keeps the time-stamp of the
1443 * returns -EAGAIN.
1447 * @return -EAGAIN if the sample was not updated yet. 0 when the sample
1463 * The HW maintains 50 bits for the sub-seconds portion in femto resolution,
1465 * sub-nanoseconds accuracy, which is not needed.
1782 /* Rx Frequency adjust FIFO input packets */
1784 /* Rx Frequency adjust FIFO input short error packets */
1786 /* Rx Frequency adjust FIFO input long error packets */
1788 /* Rx Frequency adjust FIFO output packets */
1790 /* Rx Frequency adjust FIFO output short error packets */
1792 /* Rx Frequency adjust FIFO output long error packets */
1794 /* Rx Frequency adjust FIFO output drop packets */
1796 /* Number of packets written into the Rx FIFO (without FIFO error indication) */
1798 /* Number of error packets written into the Rx FIFO (with FIFO error indication, */
1801 /* Number of packets read from Rx FIFO 1 */
1803 /* Number of packets read from Rx FIFO 2 (loopback FIFO) */
1805 /* Rx FIFO output drop packets from FIFO 1 */
1807 /* Rx FIFO output drop packets from FIFO 2 (loop back) */
1809 /* Rx FIFO output drop packets from FIFO 1 */
1811 /* Rx FIFO output drop packets from FIFO 2 (loop back) */
1813 /* Rx Parser 1, input packet counter */
1815 /* Rx Parser 1, output packet counter */
1817 /* Rx Parser 2, input packet counter */
1819 /* Rx Parser 2, output packet counter */
1821 /* Rx Parser 3 (MACsec), input packet counter */
1823 /* Rx Parser 3 (MACsec), output packet counter */
1835 /* Rx forwarding input packet counter */
1837 /* Rx Forwarding, packet with VLAN command drop indication */
1839 /* Rx Forwarding, packets with parse drop indication */
1841 /* Rx Forwarding, multicast packets */
1843 /* Rx Forwarding, broadcast packets */
1845 /* Rx Forwarding, tagged packets */
1847 /* Rx Forwarding, untagged packets */
1849 /* Rx Forwarding, packets with MAC address drop indication (from the MAC address table) */
1851 /* Rx Forwarding, packets with undetected MAC address */
1853 /* Rx Forwarding, packets with drop indication from the control table */
1855 /* Rx Forwarding, packets with L3_protocol_index drop indication */
1871 /* Rx forwarding output packet counter */
1873 /* Rx forwarding output drop packet counter */
1875 /* Multi-stream write, number of Rx packets */
1877 /* Multi-stream write, number of dropped packets at SOP, Q full indication */
1879 /* Multi-stream write, number of dropped packets at SOP */
1881 /* Multi-stream write, number of dropped packets at EOP, */
1884 …/* Multi-stream write, number of packets written to the stream FIFO with EOP and without packet lo…
1886 /* Multi-stream write, number of packets read from the FIFO into the stream */
1902 /* Tx MAC interface, number of packets forwarded to the Rx data path */
2041 al_bool autoneg_enable; /**< enable Auto-Negotiation */
2042 al_bool kr_lt_enable; /**< enable KR Link-Training */
2047 enum al_eth_board_auto_neg_mode an_mode; /**< auto-negotiation mode (in-band / out-of-band) */
2052 al_bool force_1000_base_x; /**< set mac to 1000 base-x mode (instead sgmii) */
2060 enum al_eth_retimer_channel retimer_channel; /**< what channel connected to this port (Rx) */
2093 * Wake-On-Lan (WoL)
2095 * The following few functions configure the Wake-On-Lan packet detection
2099 * external 1000Base-T transceiver to set WoL mode.
2101 * These APIs do not set the system-wide power-state, nor responsible on the
2196 * the udmas, through the Rx path (udma_mask is one-hot representation)
2216 /** Rx Generic protocol detect Cam compare table entry */
2287 /** Rx Generic crc prameters table entry */
2439 /* *INDENT-ON* */