| /freebsd-src/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | lantiq,pinctrl-xway.txt | 4 - compatible: "lantiq,<chip>-pinctrl", where <chip> is:
10 - reg: Should contain the physical address and length of the gpio/pinmux
13 Please refer to pinctrl-bindings.txt in this directory for details of the
15 phrase "pin configuration node".
17 Lantiq's pin configuration nodes act as a container for an arbitrary number of
19 pin, a group, or a list of pins or groups. This configuration can include the
20 mux function to select on those group(s), and two pin configuration parameters:
21 pull-up and open-drain
27 other words, a subnode that lists a mux function but no pin configuration
28 parameters implies no information about any pin configuration parameters.
[all …]
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| H A D | cortina,gemini-pinctrl.txt | 1 Cortina Systems Gemini pin controller
3 This pin controller is found in the Cortina Systems Gemini SoC family,
4 see further arm/gemini.txt. It is a purely group-based multiplexing pin
7 The pin controller node must be a subnode of the system controller node.
10 - compatible: "cortina,gemini-pinctrl"
12 Subnodes of the pin controller contain pin control multiplexing set-up
13 and pin configuration of individual pins.
15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
16 and generic pin config nodes.
19 - skew-delay is supported on the Ethernet pins
[all …]
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| H A D | lantiq,pinctrl-falcon.txt | 4 - compatible: "lantiq,pinctrl-falcon"
5 - reg: Should contain the physical address and length of the gpio/pinmux
8 Please refer to pinctrl-bindings.txt in this directory for details of the
10 phrase "pin configuration node".
12 Lantiq's pin configuration nodes act as a container for an arbitrary number of
14 pin, a group, or a list of pins or groups. This configuration can include the
15 mux function to select on those group(s), and two pin configuration parameters:
16 pull-up and open-drain
22 other words, a subnode that lists a mux function but no pin configuration
23 parameters implies no information about any pin configuration parameters.
[all …]
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| H A D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
15 used for a specific device or function. This node represents both mux and config
16 of the pins in that group. The 'mux' selects the function mode(also named mux
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
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| H A D | fsl,mxs-pinctrl.txt | 1 * Freescale MXS Pin Controller
3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
11 pin controller.
13 Please refer to pinctrl-bindings.txt in this directory for details of the
16 The node of mxs pin controller acts as a container for an arbitrary number of
20 information about pull-up. For this reason, even seemingly boolean values are
[all …]
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| H A D | qcom,msm8974-pinctrl.txt | 4 - compatible: "qcom,msm8974-pinctrl"
5 - reg: Should be the base address and length of the TLMM block.
6 - interrupts: Should be the parent IRQ of the TLMM block.
7 - interrupt-controller: Marks the device node as an interrupt controller.
8 - #interrupt-cells: Should be two.
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
13 - gpio-ranges: see ../gpio/gpio.txt
17 - gpio-reserved-ranges: see ../gpio/gpio.txt
[all …]
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| H A D | qcom,ipq8064-pinctrl.txt | 4 - compatible: "qcom,ipq8064-pinctrl"
5 - reg: Should be the base address and length of the TLMM block.
6 - interrupts: Should be the parent IRQ of the TLMM block.
7 - interrupt-controller: Marks the device node as an interrupt controller.
8 - #interrupt-cells: Should be two.
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
13 - gpio-ranges: see ../gpio/gpio.txt
17 - gpio-reserved-ranges: see ../gpio/gpio.txt
[all …]
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| H A D | qcom,ipq4019-pinctrl.txt | 7 - compatible: "qcom,ipq4019-pinctrl"
8 - reg: Should be the base address and length of the TLMM block.
9 - interrupts: Should be the parent IRQ of the TLMM block.
10 - interrupt-controller: Marks the device node as an interrupt controller.
11 - #interrupt-cells: Should be two.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells : Should be two.
14 The first cell is the gpio pin number and the
16 - gpio-ranges: see ../gpio/gpio.txt
20 - gpio-reserved-ranges: see ../gpio/gpio.txt
[all …]
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| H A D | nvidia,tegra20-pinmux.txt | 4 - compatible: "nvidia,tegra20-pinmux"
5 - reg: Should contain the register physical address and length for each of
6 the tri-state, mux, pull-up/down, and pad control register sets.
8 Please refer to pinctrl-bindings.txt in this directory for details of the
10 phrase "pin configuration node".
12 Tegra's pin configuration nodes act as a container for an arbitrary number of
14 pin, a group, or a list of pins or groups. This configuration can include the
15 mux function to select on those pin(s)/group(s), and various pin configuration
16 parameters, such as pull-up, tristate, drive strength, etc.
22 other words, a subnode that lists a mux function but no pin configuration
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| H A D | pinctrl-vt8500.txt | 1 VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
3 These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
7 - compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
8 "wm8750-pinctrl" or "wm,wm8850-pinctrl"
9 - reg: Should contain the physical address of the module's registers.
10 - interrupt-controller: Marks the device node as an interrupt controller.
11 - #interrupt-cells: Should be two.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 bit 0 - active low
[all …]
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| H A D | nvidia,tegra210-pinmux.txt | 4 - compatible: "nvidia,tegra210-pinmux"
5 - reg: Should contain a list of base address and size pairs for:
6 - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7 - second entry: The PINMUX_AUX_* registers (pinmux)
9 Please refer to pinctrl-bindings.txt in this directory for details of the
11 phrase "pin configuration node".
13 Tegra's pin configuration nodes act as a container for an arbitrary number of
15 pin, a group, or a list of pins or groups. This configuration can include the
16 mux function to select on those pin(s)/group(s), and various pin configuration
17 parameters, such as pull-up, tristate, drive strength, etc.
[all …]
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| H A D | pinmux-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Multiplexing Node
10 - Linus Walleij <linus.walleij@linaro.org>
13 The contents of the pin configuration child nodes are defined by the binding
14 for the individual pin controller device. The pin configuration nodes need not
15 be direct children of the pin controller device; they may be grandchildren,
18 the binding for the individual pin controller device.
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| H A D | sunplus,sp7021-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus SP7021 Pin Controller
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
23 (1) function-group pins:
[all …]
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| H A D | nvidia,tegra194-pinmux.txt | 4 - compatible: "nvidia,tegra194-pinmux"
5 - reg: Should contain a list of base address and size pairs for:
6 - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7 - second entry: The PINMUX_AUX_* registers (pinmux)
9 Please refer to pinctrl-bindings.txt in this directory for details of the
11 phrase "pin configuration node".
13 Tegra's pin configuration nodes act as a container for an arbitrary number of
15 pin, a group, or a list of pins or groups. This configuration can include the
16 mux function to select on those pin(s)/group(s), and various pin configuration
17 parameters, such as pull-up, tristate, drive strength, etc.
[all …]
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| H A D | qcom,msm8976-pinctrl.txt | 6 - compatible:
9 Definition: must be "qcom,msm8976-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
26 - #interrupt-cells:
29 Definition: must be 2. Specifying the pin number and flags, as defined
30 in <dt-bindings/interrupt-controller/irq.h>
[all …]
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| H A D | qcom,msm8660-pinctrl.txt | 4 - compatible: "qcom,msm8660-pinctrl"
5 - reg: Should be the base address and length of the TLMM block.
6 - interrupts: Should be the parent IRQ of the TLMM block.
7 - interrupt-controller: Marks the device node as an interrupt controller.
8 - #interrupt-cells: Should be two.
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
13 - gpio-ranges: see ../gpio/gpio.txt
17 - gpio-reserved-ranges: see ../gpio/gpio.txt
[all …]
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| H A D | qcom,apq8064-pinctrl.txt | 4 - compatible: "qcom,apq8064-pinctrl"
5 - reg: Should be the base address and length of the TLMM block.
6 - interrupts: Should be the parent IRQ of the TLMM block.
7 - interrupt-controller: Marks the device node as an interrupt controller.
8 - #interrupt-cells: Should be two.
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
13 - gpio-ranges: see ../gpio/gpio.txt
17 - gpio-reserved-ranges: see ../gpio/gpio.txt
[all …]
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| H A D | qcom,sdm845-pinctrl.txt | 6 - compatible:
9 Definition: must be "qcom,sdm845-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
26 - #interrupt-cells:
29 Definition: must be 2. Specifying the pin number and flags, as defined
30 in <dt-bindings/interrupt-controller/irq.h>
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| H A D | brcm,bcm11351-pinctrl.txt | 1 Broadcom BCM281xx Pin Controller
3 This is a pin controller for the Broadcom BCM281xx SoC family, which includes
6 === Pin Controller Node ===
10 - compatible: Must be "brcm,bcm11351-pinctrl"
11 - reg: Base address of the PAD Controller register block and the size
17 compatible = "brcm,bcm11351-pinctrl";
21 As a pin controller device, in addition to the required properties, this node
22 should also contain the pin configuration nodes that client devices reference,
25 === Pin Configuration Node ===
27 Each pin configuration node is a sub-node of the pin controller node and is a
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| H A D | rockchip,pinctrl.txt | 8 Please refer to pinctrl-bindings.txt in this directory for details of the
10 phrase "pin configuration node".
12 The Rockchip pin configuration node is a node of a group of pins which can be
13 used for a specific device or function. This node represents both mux and
15 named pin mode) this pin can work on and the 'config' configures various pad
16 settings such as pull-up, etc.
18 The pins are grouped into up to 5 individual pin banks which need to be
19 defined as gpio sub-nodes of the pinmux controller.
22 - compatible: should be
23 "rockchip,px30-pinctrl": for Rockchip PX30
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| H A D | brcm,bcm2835-gpio.txt | 7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
[all …]
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| /freebsd-src/sys/contrib/device-tree/Bindings/mux/ |
| H A D | gpio-mux.txt | 1 GPIO-based multiplexer controller bindings
7 - compatible : "gpio-mux"
8 - mux-gpios : list of gpios used to control the multiplexer, least
10 - #mux-control-cells : <0>
11 * Standard mux-controller bindings as decribed in mux-controller.txt
14 - idle-state : if present, the state the mux will have when idle. The
18 multiplexer GPIO pins, where the first pin is the least significant
19 bit. An active pin is a binary 1, an inactive pin is a binary 0.
23 mux: mux-controller {
24 compatible = "gpio-mux";
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| H A D | gpio-mux.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/gpio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
17 multiplexer GPIO pins, where the first pin is the least significant
18 bit. An active pin is a binary 1, an inactive pin is a binary 0.
22 const: gpio-mux
24 mux-gpios:
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| /freebsd-src/sys/contrib/device-tree/Bindings/display/msm/ |
| H A D | hdmi.txt | 4 - compatible: one of the following
5 * "qcom,hdmi-tx-8996"
6 * "qcom,hdmi-tx-8994"
7 * "qcom,hdmi-tx-8084"
8 * "qcom,hdmi-tx-8974"
9 * "qcom,hdmi-tx-8660"
10 * "qcom,hdmi-tx-8960"
11 - reg: Physical base address and length of the controller's registers
12 - reg-names: "core_physical"
13 - interrupts: The interrupt signal from the hdmi block.
[all …]
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| /freebsd-src/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | omap-usb-host.txt | 5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
[all …]
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