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/freebsd-src/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,qmp-phy.yaml5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
8 title: Qualcomm QMP PHY controller
14 QMP phy controller supports physical layer functionality for a number of
20 - qcom,ipq6018-qmp-pcie-phy
21 - qcom,ipq6018-qmp-usb3-phy
22 - qcom,ipq8074-qmp-gen3-pcie-phy
23 - qcom,ipq8074-qmp-pcie-phy
24 - qcom,ipq8074-qmp-usb3-phy
25 - qcom,msm8996-qmp-pcie-phy
26 - qcom,msm8996-qmp-ufs-phy
[all …]
H A Dsamsung-phy.txt6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
14 In case of exynos5433 compatible PHY:
20 For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
21 the PHY specifier identifies the PHY and its meaning is as follows:
26 "samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy"
27 supports additional fifth PHY:
30 Samsung Exynos SoC series Display Port PHY
[all …]
H A Dqcom,qmp-usb-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,qmp-usb-phy.yaml#
7 title: Qualcomm QMP PHY controller (USB)
13 QMP PHY controller supports physical layer functionality for a number of
19 - qcom,ipq6018-qmp-usb3-phy
20 - qcom,ipq8074-qmp-usb3-phy
21 - qcom,msm8996-qmp-usb3-phy
22 - qcom,msm8998-qmp-usb3-phy
23 - qcom,qcm2290-qmp-usb3-phy
24 - qcom,sc7180-qmp-usb3-phy
25 - qcom,sc8180x-qmp-usb3-phy
[all …]
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
22 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
23 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
24 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
[all...]
H A Dqcom,qmp-pcie-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
7 title: Qualcomm QMP PHY controller (PCIe)
13 QMP PHY controller supports physical layer functionality for a number of
19 - qcom,ipq6018-qmp-pcie-phy
20 - qcom,ipq8074-qmp-gen3-pcie-phy
21 - qcom,ipq8074-qmp-pcie-phy
22 - qcom,msm8998-qmp-pcie-phy
23 - qcom,sc8180x-qmp-pcie-phy
24 - qcom,sdm845-qhp-pcie-phy
25 - qcom,sdm845-qmp-pcie-phy
[all …]
H A Dqcom,sc8280xp-qmp-ufs-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
7 title: Qualcomm QMP PHY controller (UFS, SC8280XP)
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
21 - qcom,sa8775p-qmp-ufs-phy
22 - qcom,sc7180-qmp-ufs-phy
23 - qcom,sc7280-qmp-ufs-phy
24 - qcom,sc8180x-qmp-ufs-phy
[all...]
H A Dqcom,sc8280xp-qmp-usb3-uni-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml#
7 title: Qualcomm QMP PHY controller (USB, SC8280XP)
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,ipq6018-qmp-usb3-phy
20 - qcom,ipq8074-qmp-usb3-phy
21 - qcom,ipq9574-qmp-usb3-phy
22 - qcom,msm8996-qmp-usb3-phy
23 - qcom,qdu1000-qmp-usb3-uni-phy
24 - qcom,sa8775p-qmp-usb3-uni-phy
[all...]
H A Dqcom,qmp-ufs-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml#
7 title: Qualcomm QMP PHY controller (UFS)
13 QMP PHY controller supports physical layer functionality for a number of
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
21 - qcom,sc8180x-qmp-ufs-phy
22 - qcom,sc8280xp-qmp-ufs-phy
23 - qcom,sdm845-qmp-ufs-phy
24 - qcom,sm6115-qmp-ufs-phy
25 - qcom,sm6350-qmp-ufs-phy
[all …]
H A Dqcom,msm8996-qmp-usb3-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-usb3-phy.yaml#
7 title: Qualcomm QMP PHY controller (USB, MSM8996)
13 QMP PHY controller supports physical layer functionality for a number of
17 qcom,sc8280xp-qmp-usb3-uni-phy.yaml.
22 - qcom,ipq6018-qmp-usb3-phy
23 - qcom,ipq8074-qmp-usb3-phy
24 - qcom,msm8996-qmp-usb3-phy
25 - qcom,msm8998-qmp-usb3-phy
26 - qcom,sdm845-qmp-usb3-uni-phy
27 - qcom,sdx55-qmp-usb3-uni-phy
[all …]
H A Dqcom,msm8996-qmp-ufs-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-ufs-phy.yaml#
7 title: Qualcomm QMP PHY controller (UFS, MSM8996)
13 QMP PHY controller supports physical layer functionality for a number of
17 qcom,sc8280xp-qmp-ufs-phy.yaml.
22 - qcom,msm8996-qmp-ufs-phy
23 - qcom,msm8998-qmp-ufs-phy
24 - qcom,sc8180x-qmp-ufs-phy
25 - qcom,sdm845-qmp-ufs-phy
26 - qcom,sm6115-qmp-ufs-phy
27 - qcom,sm6350-qmp-ufs-phy
[all …]
H A Dbrcm-sata-phy.txt1 * Broadcom SATA3 PHY
5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
15 - reg: register ranges for the PHY PCB interface
[all …]
H A Dqcom,sc7180-qmp-usb3-dp-phy.yaml5 $id: http://devicetree.org/schemas/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml#
8 title: Qualcomm QMP USB3 DP PHY controller (SC7180)
11 The QMP PHY controller supports physical layer functionality for a number of
15 qcom,sc8280xp-qmp-usb43dp-phy.yaml.
24 - qcom,sc7180-qmp-usb3-dp-phy
25 - qcom,sc8180x-qmp-usb3-dp-phy
26 - qcom,sdm845-qmp-usb3-dp-phy
27 - qcom,sm8250-qmp-usb3-dp-phy
30 - qcom,sc7280-qmp-usb3-dp-phy
31 - const: qcom,sm8250-qmp-usb3-dp-phy
[all …]
H A Dqcom,sc8280xp-qmp-usb43dp-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,sc7180-qmp-usb3-dp-phy
20 - qcom,sc7280-qmp-usb3-dp-phy
21 - qcom,sc8180x-qmp-usb3-dp-phy
22 - qcom,sc8280xp-qmp-usb43dp-phy
23 - qcom,sdm845-qmp-usb3-dp-phy
24 - qcom,sm6350-qmp-usb3-dp-phy
25 - qcom,sm8150-qmp-usb3-dp-phy
[all …]
H A Drealtek,usb2phy.yaml5 $id: http://devicetree.org/schemas/phy/realtek,usb2phy.yaml#
8 title: Realtek DHC SoCs USB 2.0 PHY
14 Realtek USB 2.0 PHY support the digital home center (DHC) RTD series SoCs.
15 The USB 2.0 PHY driver is designed to support the XHCI controller. The SoCs
16 support multiple XHCI controllers. One PHY device node maps to one XHCI
21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
23 XHCI controller#0 -- usb2phy -- phy#0
24 |- usb3phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/microchip/
H A Dsparx5_pcb135_board.dtsi202 phy0: ethernet-phy@0 {
205 phy1: ethernet-phy@1 {
208 phy2: ethernet-phy@2 {
211 phy3: ethernet-phy@3 {
214 phy4: ethernet-phy@4 {
217 phy5: ethernet-phy@5 {
220 phy6: ethernet-phy@6 {
223 phy7: ethernet-phy@7 {
226 phy8: ethernet-phy@8 {
229 phy9: ethernet-phy
[all...]
/freebsd-src/sys/dev/isci/scil/
H A Dscic_sds_phy_registers.h60 * @brief This file contains the macros used by the phy object to read/write
75 * Macro to read the transport layer register associated with this phy
78 #define scu_transport_layer_read(phy, reg) \ argument
80 scic_sds_phy_get_controller(phy), \
81 (phy)->transport_layer_registers->reg \
85 * Macro to write the transport layer register associated with this phy
88 #define scu_transport_layer_write(phy, reg, value) \ argument
90 scic_sds_phy_get_controller(phy), \
91 (phy)->transport_layer_registers->reg, \
96 //* Transport Layer registers controlled by the phy object
[all …]
H A Dscic_phy.h61 * by an SCIC user on a phy (SAS or SATA) object.
84 * supplied phy. This field may be set to SCI_INVALID_HANDLE
85 * if the phy is not currently contained in a port.
90 * This field specifies the maximum link rate for which this phy
96 * This field specifies the link rate at which the phy is
103 * transmitted to the connected phy.
108 * This field specifies the index of the phy in relation to other
118 * SAS phy, that can be retrieved.
129 * This field delineates the Phy capabilities structure received
139 * SATA phy, that can be retrieved.
[all …]
/freebsd-src/sys/dev/e1000/
H A De1000_phy.c65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
72 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_ops_generic() local
76 phy->ops.init_params = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
77 phy->ops.acquire = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
78 phy->ops.check_polarity = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
79 phy->ops.check_reset_block = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
80 phy->ops.commit = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
81 phy->ops.force_speed_duplex = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
82 phy in e1000_init_phy_ops_generic()
226 struct e1000_phy_info *phy = &hw->phy; e1000_get_phy_id() local
292 struct e1000_phy_info *phy = &hw->phy; e1000_read_phy_reg_mdic() local
357 struct e1000_phy_info *phy = &hw->phy; e1000_write_phy_reg_mdic() local
423 struct e1000_phy_info *phy = &hw->phy; e1000_read_phy_reg_i2c() local
470 struct e1000_phy_info *phy = &hw->phy; e1000_write_phy_reg_i2c() local
1121 struct e1000_phy_info *phy = &hw->phy; e1000_copper_link_setup_m88() local
1274 struct e1000_phy_info *phy = &hw->phy; e1000_copper_link_setup_m88_gen2() local
1372 struct e1000_phy_info *phy = &hw->phy; e1000_copper_link_setup_igp() local
1483 struct e1000_phy_info *phy = &hw->phy; e1000_phy_setup_autoneg() local
1636 struct e1000_phy_info *phy = &hw->phy; e1000_copper_link_autoneg() local
1753 struct e1000_phy_info *phy = &hw->phy; e1000_phy_force_speed_duplex_igp() local
1819 struct e1000_phy_info *phy = &hw->phy; e1000_phy_force_speed_duplex_m88() local
1958 struct e1000_phy_info *phy = &hw->phy; e1000_phy_force_speed_duplex_ife() local
2089 struct e1000_phy_info *phy = &hw->phy; e1000_set_d3_lplu_state_generic() local
2173 struct e1000_phy_info *phy = &hw->phy; e1000_check_downshift_generic() local
2218 struct e1000_phy_info *phy = &hw->phy; e1000_check_polarity_m88() local
2245 struct e1000_phy_info *phy = &hw->phy; e1000_check_polarity_igp() local
2288 struct e1000_phy_info *phy = &hw->phy; e1000_check_polarity_ife() local
2419 struct e1000_phy_info *phy = &hw->phy; e1000_get_cable_length_m88() local
2445 struct e1000_phy_info *phy = &hw->phy; e1000_get_cable_length_m88_gen2() local
2568 struct e1000_phy_info *phy = &hw->phy; e1000_get_cable_length_igp_2() local
2638 struct e1000_phy_info *phy = &hw->phy; e1000_get_phy_info_m88() local
2713 struct e1000_phy_info *phy = &hw->phy; e1000_get_phy_info_igp() local
2775 struct e1000_phy_info *phy = &hw->phy; e1000_get_phy_info_ife() local
2863 struct e1000_phy_info *phy = &hw->phy; e1000_phy_hw_reset_generic() local
3892 struct e1000_phy_info *phy = &hw->phy; e1000_check_polarity_82577() local
3916 struct e1000_phy_info *phy = &hw->phy; e1000_phy_force_speed_duplex_82577() local
3965 struct e1000_phy_info *phy = &hw->phy; e1000_get_phy_info_82577() local
4028 struct e1000_phy_info *phy = &hw->phy; e1000_get_cable_length_82577() local
[all...]
/freebsd-src/sys/dev/igc/
H A Digc_phy.c13 * igc_init_phy_ops_generic - Initialize PHY function pointers
20 struct igc_phy_info *phy = &hw->phy; in igc_init_phy_ops_generic() local
24 phy->ops.init_params = igc_null_ops_generic; in igc_init_phy_ops_generic()
25 phy->ops.acquire = igc_null_ops_generic; in igc_init_phy_ops_generic()
26 phy->ops.check_reset_block = igc_null_ops_generic; in igc_init_phy_ops_generic()
27 phy->ops.force_speed_duplex = igc_null_ops_generic; in igc_init_phy_ops_generic()
28 phy->ops.get_info = igc_null_ops_generic; in igc_init_phy_ops_generic()
29 phy->ops.set_page = igc_null_set_page; in igc_init_phy_ops_generic()
30 phy->ops.read_reg = igc_null_read_reg; in igc_init_phy_ops_generic()
31 phy->ops.read_reg_locked = igc_null_read_reg; in igc_init_phy_ops_generic()
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls2088a-rdb.dts27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
37 phy-handle = <&mdio1_phy3>;
38 phy-connection-type = "10gbase-r";
42 phy-handle = <&mdio1_phy4>;
43 phy-connection-type = "10gbase-r";
47 phy-handle = <&mdio2_phy1>;
48 phy-connection-type = "10gbase-r";
[all …]
/freebsd-src/sys/dev/etherswitch/ar40xx/
H A Dar40xx_phy.c82 int phy; in ar40xx_phy_tick() local
89 * Loop over; update phy port status here in ar40xx_phy_tick()
91 for (phy = 0; phy < AR40XX_NUM_PHYS; phy++) { in ar40xx_phy_tick()
93 * Port here is PHY, not port! in ar40xx_phy_tick()
95 reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(phy + 1)); in ar40xx_phy_tick()
97 mii = device_get_softc(sc->sc_phys.miibus[phy]); in ar40xx_phy_tick()
101 * status. We may need to clear ATU / change phy config. in ar40xx_phy_tick()
106 "%s: PHY %d: down -> up\n", __func__, phy); in ar40xx_phy_tick()
107 ar40xx_hw_port_link_up(sc, phy + 1); in ar40xx_phy_tick()
108 ar40xx_hw_atu_flush_port(sc, phy + 1); in ar40xx_phy_tick()
[all …]
/freebsd-src/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dtestmode.c38 mt7915_tm_set_tx_power(struct mt7915_phy *phy) in mt7915_tm_set_tx_power() argument
40 struct mt7915_dev *dev = phy->dev; in mt7915_tm_set_tx_power()
41 struct mt76_phy *mphy = phy->mt76; in mt7915_tm_set_tx_power()
54 .band_idx = phy->mt76->band_idx, in mt7915_tm_set_tx_power()
59 if (phy->mt76->test.state != MT76_TM_STATE_OFF) in mt7915_tm_set_tx_power()
60 tx_power = phy->mt76->test.tx_power; in mt7915_tm_set_tx_power()
74 mt7915_tm_set_freq_offset(struct mt7915_phy *phy, bool en, u32 val) in mt7915_tm_set_freq_offset() argument
76 struct mt7915_dev *dev = phy->dev; in mt7915_tm_set_freq_offset()
80 .param.freq.band = phy->mt76->band_idx, in mt7915_tm_set_freq_offset()
106 mt7915_tm_set_trx(struct mt7915_phy *phy, int type, bool en) in mt7915_tm_set_trx() argument
[all …]
/freebsd-src/sys/contrib/dev/mediatek/mt76/
H A Dmac80211.c206 static int mt76_led_init(struct mt76_phy *phy) in mt76_led_init() argument
208 struct mt76_dev *dev = phy->dev; in mt76_led_init()
209 struct ieee80211_hw *hw = phy->hw; in mt76_led_init()
211 if (!phy->leds.cdev.brightness_set && !phy->leds.cdev.blink_set) in mt76_led_init()
214 snprintf(phy->leds.name, sizeof(phy->leds.name), "mt76-%s", in mt76_led_init()
217 phy->leds.cdev.name = phy->leds.name; in mt76_led_init()
218 phy->leds.cdev.default_trigger = in mt76_led_init()
225 if (phy == &dev->phy) { in mt76_led_init()
233 phy->leds.pin = led_pin; in mt76_led_init()
234 phy->leds.al = of_property_read_bool(np, in mt76_led_init()
[all …]
/freebsd-src/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmain.c17 struct mt7615_phy *phy; in mt7615_dev_running() local
22 phy = mt7615_ext_phy(dev); in mt7615_dev_running()
24 return phy && test_bit(MT76_STATE_RUNNING, &phy->mt76->state); in mt7615_dev_running()
30 struct mt7615_phy *phy = mt7615_hw_phy(hw); in mt7615_start() local
54 if (phy != &dev->phy) { in mt7615_start()
67 ret = mt76_connac_mcu_set_channel_domain(phy->mt76); in mt7615_start()
71 ret = mt76_connac_mcu_set_rate_txpower(phy->mt76); in mt7615_start()
76 ret = mt7615_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH)); in mt7615_start()
80 set_bit(MT76_STATE_RUNNING, &phy->mt76->state); in mt7615_start()
83 ieee80211_queue_delayed_work(hw, &phy->mt76->mac_work, timeout); in mt7615_start()
[all …]
/freebsd-src/sys/dev/cxgb/common/
H A Dcxgb_aq100x.c66 #define AQ_WRITE_REGS(phy, regs) do { \ argument
69 (void) mdio_write(phy, regs[i].mmd, regs[i].reg, regs[i].val); \
72 #define AQ_READ_REGS(phy, regs) do { \ argument
75 (void) mdio_read(phy, regs[i].mmd, regs[i].reg, &v); \
83 aq100x_temperature(struct cphy *phy) in aq100x_temperature() argument
87 if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL2, &v) || in aq100x_temperature()
91 if (mdio_read(phy, MDIO_DEV_VEND1, AQ_THERMAL1, &v)) in aq100x_temperature()
98 aq100x_set_defaults(struct cphy *phy) in aq100x_set_defaults() argument
100 return mdio_write(phy, MDIO_DEV_VEND1, AQ_THERMAL_THR, 0x6c00); in aq100x_set_defaults()
104 aq100x_reset(struct cphy *phy, int wait) in aq100x_reset() argument
[all …]

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