Lines Matching full:phy
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
72 struct e1000_phy_info *phy = &hw->phy;
76 phy->ops.init_params = e1000_null_ops_generic;
77 phy->ops.acquire = e1000_null_ops_generic;
78 phy->ops.check_polarity = e1000_null_ops_generic;
79 phy->ops.check_reset_block = e1000_null_ops_generic;
80 phy->ops.commit = e1000_null_ops_generic;
81 phy->ops.force_speed_duplex = e1000_null_ops_generic;
82 phy->ops.get_cfg_done = e1000_null_ops_generic;
83 phy->ops.get_cable_length = e1000_null_ops_generic;
84 phy->ops.get_info = e1000_null_ops_generic;
85 phy->ops.set_page = e1000_null_set_page;
86 phy->ops.read_reg = e1000_null_read_reg;
87 phy->ops.read_reg_locked = e1000_null_read_reg;
88 phy->ops.read_reg_page = e1000_null_read_reg;
89 phy->ops.release = e1000_null_phy_generic;
90 phy->ops.reset = e1000_null_ops_generic;
91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
93 phy->ops.write_reg = e1000_null_write_reg;
94 phy->ops.write_reg_locked = e1000_null_write_reg;
95 phy->ops.write_reg_page = e1000_null_write_reg;
96 phy->ops.power_up = e1000_null_phy_generic;
97 phy->ops.power_down = e1000_null_phy_generic;
98 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
99 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
100 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
198 * e1000_check_reset_block_generic - Check if PHY reset is blocked
201 * Read the PHY management control register and check whether a PHY reset
218 * e1000_get_phy_id - Retrieve the PHY ID and revision
221 * Reads the PHY registers and stores the PHY ID and possibly the PHY
226 struct e1000_phy_info *phy = &hw->phy;
233 if (!phy->ops.read_reg)
237 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
241 phy->id = (u32)(phy_id << 16);
243 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
247 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
248 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
250 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
260 * e1000_phy_reset_dsp_generic - Reset PHY DSP
271 if (!hw->phy.ops.write_reg)
274 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
278 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
287 * Reads the MDI control register in the PHY at offset and stores the
292 struct e1000_phy_info *phy = &hw->phy;
298 DEBUGOUT1("PHY Address %d is out of range\n", offset);
302 /* Set up Op-code, Phy Address, and register offset in the MDI
304 * PHY to retrieve the desired data.
307 (phy->addr << E1000_MDIC_PHY_SHIFT) |
353 * Writes data to MDI control register in the PHY at offset.
357 struct e1000_phy_info *phy = &hw->phy;
363 DEBUGOUT1("PHY Address %d is out of range\n", offset);
367 /* Set up Op-code, Phy Address, and register offset in the MDI
369 * PHY to retrieve the desired data.
373 (phy->addr << E1000_MDIC_PHY_SHIFT) |
413 * e1000_read_phy_reg_i2c - Read PHY register using i2c
418 * Reads the PHY register at offset using the i2c interface and stores the
423 struct e1000_phy_info *phy = &hw->phy;
428 /* Set up Op-code, Phy Address, and register address in the I2CCMD
430 * PHY to retrieve the desired data.
433 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
461 * e1000_write_phy_reg_i2c - Write PHY register using i2c
466 * Writes the data to PHY register at the offset using the i2c interface.
470 struct e1000_phy_info *phy = &hw->phy;
477 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
478 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
479 hw->phy.addr);
486 /* Set up Op-code, Phy Address, and register address in the I2CCMD
488 * PHY to retrieve the desired data.
491 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
645 * e1000_read_phy_reg_m88 - Read m88 PHY register
650 * Acquires semaphore, if necessary, then reads the PHY register at offset
660 if (!hw->phy.ops.acquire)
663 ret_val = hw->phy.ops.acquire(hw);
670 hw->phy.ops.release(hw);
676 * e1000_write_phy_reg_m88 - Write m88 PHY register
681 * Acquires semaphore, if necessary, then writes the data to PHY register
690 if (!hw->phy.ops.acquire)
693 ret_val = hw->phy.ops.acquire(hw);
700 hw->phy.ops.release(hw);
706 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
710 * Sets PHY page required for PHY register access. Assumes semaphore is
711 * already acquired. Note, this function sets phy.addr to 1 so the caller
720 hw->phy.addr = 1;
726 * __e1000_read_phy_reg_igp - Read igp PHY register
732 * Acquires semaphore, if necessary, then reads the PHY register at offset
744 if (!hw->phy.ops.acquire)
747 ret_val = hw->phy.ops.acquire(hw);
761 hw->phy.ops.release(hw);
767 * e1000_read_phy_reg_igp - Read igp PHY register
772 * Acquires semaphore then reads the PHY register at offset and stores the
782 * e1000_read_phy_reg_igp_locked - Read igp PHY register
787 * Reads the PHY register at offset and stores the retrieved information
796 * e1000_write_phy_reg_igp - Write igp PHY register
802 * Acquires semaphore, if necessary, then writes the data to PHY register
813 if (!hw->phy.ops.acquire)
816 ret_val = hw->phy.ops.acquire(hw);
830 hw->phy.ops.release(hw);
836 * e1000_write_phy_reg_igp - Write igp PHY register
841 * Acquires semaphore then writes the data to PHY register
850 * e1000_write_phy_reg_igp_locked - Write igp PHY register
855 * Writes the data to PHY register at the offset.
870 * Acquires semaphore, if necessary. Then reads the PHY register at offset
884 if (!hw->phy.ops.acquire)
887 ret_val = hw->phy.ops.acquire(hw);
903 hw->phy.ops.release(hw);
914 * Acquires semaphore then reads the PHY register at offset using the
929 * Reads the PHY register at offset using the kumeran interface. The
945 * Acquires semaphore, if necessary. Then write the data to PHY register
959 if (!hw->phy.ops.acquire)
962 ret_val = hw->phy.ops.acquire(hw);
975 hw->phy.ops.release(hw);
986 * Acquires semaphore then writes the data to the PHY register at the offset
1000 * Write the data to PHY register at the offset using the kumeran interface.
1009 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
1020 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1025 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1030 switch (hw->phy.ms_type) {
1045 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1049 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1061 if (hw->phy.type == e1000_phy_82580) {
1062 ret_val = hw->phy.ops.reset(hw);
1064 DEBUGOUT("Error resetting the PHY.\n");
1070 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1079 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1084 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1093 switch (hw->phy.mdix) {
1105 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1113 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1116 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1121 struct e1000_phy_info *phy = &hw->phy;
1129 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1133 /* For BM PHY this bit is downshift enable */
1134 if (phy->type != e1000_phy_bm)
1146 switch (phy->mdix) {
1170 if (phy->disable_polarity_correction)
1174 if (phy->type == e1000_phy_bm) {
1176 if (phy->id == BME1000_E_PHY_ID_R2) {
1178 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1183 ret_val = phy->ops.commit(hw);
1185 DEBUGOUT("Error committing the PHY changes\n");
1193 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1197 if ((phy->type == e1000_phy_m88) &&
1198 (phy->revision < E1000_REVISION_4) &&
1199 (phy->id != BME1000_E_PHY_ID_R2)) {
1200 /* Force TX_CLK in the Extended PHY Specific Control Register
1203 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1210 if ((phy->revision == E1000_REVISION_2) &&
1211 (phy->id == M88E1111_I_PHY_ID)) {
1212 /* 82573L PHY - set the downshift counter to 5x. */
1222 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1228 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1229 /* Set PHY page 0, register 29 to 0x0003 */
1230 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1234 /* Set PHY page 0, register 30 to 0x0000 */
1235 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1241 ret_val = phy->ops.commit(hw);
1243 DEBUGOUT("Error committing the PHY changes\n");
1247 if (phy->type == e1000_phy_82578) {
1248 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1253 /* 82578 PHY - set the downshift count to 1x. */
1256 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1266 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1269 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1274 struct e1000_phy_info *phy = &hw->phy;
1282 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1295 switch (phy->mdix) {
1304 if (phy->id != M88E1112_E_PHY_ID) {
1323 if (phy->disable_polarity_correction)
1327 if (phy->id == M88E1543_E_PHY_ID) {
1330 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1334 ret_val = phy->ops.commit(hw);
1336 DEBUGOUT("Error committing the PHY changes\n");
1345 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1350 ret_val = phy->ops.commit(hw);
1352 DEBUGOUT("Error committing the PHY changes\n");
1364 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1368 * igp PHY's.
1372 struct e1000_phy_info *phy = &hw->phy;
1379 ret_val = hw->phy.ops.reset(hw);
1381 DEBUGOUT("Error resetting the PHY.\n");
1385 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1393 if (phy->type == e1000_phy_igp) {
1395 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1403 if (hw->phy.ops.set_d0_lplu_state) {
1404 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1411 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1417 switch (phy->mdix) {
1430 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1440 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1442 ret_val = phy->ops.read_reg(hw,
1449 ret_val = phy->ops.write_reg(hw,
1456 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1461 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1473 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1477 * register and if the PHY is already setup for auto-negotiation, then
1483 struct e1000_phy_info *phy = &hw->phy;
1490 phy->autoneg_advertised &= phy->autoneg_mask;
1493 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1497 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1499 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1506 * the appropriate PHY registers. First we will parse for
1522 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1525 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1531 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1537 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1543 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1548 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1549 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1553 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1559 * setup the PHY advertisement registers accordingly. If
1612 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1618 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1619 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1630 * configure to advertise the full capability. Setup the PHY to autoneg
1636 struct e1000_phy_info *phy = &hw->phy;
1645 phy->autoneg_advertised &= phy->autoneg_mask;
1650 if (!phy->autoneg_advertised)
1651 phy->autoneg_advertised = phy->autoneg_mask;
1662 * the Auto Neg Restart bit in the PHY control register.
1664 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1669 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1676 if (phy->autoneg_wait_to_complete) {
1714 /* PHY will be set to 10H, 10F, 100H or 100F
1718 ret_val = hw->phy.ops.force_speed_duplex(hw);
1745 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1748 * Calls the PHY setup function to force speed and duplex. Clears the
1754 struct e1000_phy_info *phy = &hw->phy;
1761 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1767 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1774 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1781 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1789 if (phy->autoneg_wait_to_complete) {
1790 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1809 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1812 * Calls the PHY setup function to force speed and duplex. Clears the
1813 * auto-crossover to force MDI manually. Resets the PHY to commit the
1820 struct e1000_phy_info *phy = &hw->phy;
1828 if (phy->type != e1000_phy_i210) {
1832 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1838 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1846 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1852 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1856 /* Reset the phy to commit changes. */
1857 ret_val = hw->phy.ops.commit(hw);
1861 if (phy->autoneg_wait_to_complete) {
1862 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1872 switch (hw->phy.id) {
1882 if (hw->phy.type != e1000_phy_m88)
1893 ret_val = phy->ops.write_reg(hw,
1911 if (hw->phy.type != e1000_phy_m88)
1914 if (hw->phy.id == I347AT4_E_PHY_ID ||
1915 hw->phy.id == M88E1340M_E_PHY_ID ||
1916 hw->phy.id == M88E1112_E_PHY_ID)
1918 if (hw->phy.id == I210_I_PHY_ID)
1920 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1921 (hw->phy.id == M88E1512_E_PHY_ID))
1923 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1927 /* Resetting the phy means we need to re-force TX_CLK in the
1928 * Extended PHY Specific Control Register to 25MHz clock from
1932 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1939 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1944 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1950 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1953 * Forces the speed and duplex settings of the PHY.
1955 * PHY setup routines.
1959 struct e1000_phy_info *phy = &hw->phy;
1966 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1972 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1977 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1984 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1992 if (phy->autoneg_wait_to_complete) {
1993 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
2014 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2018 * Forces speed and duplex on the PHY by doing the following: disable flow
2043 /* Disable autoneg on the phy */
2090 struct e1000_phy_info *phy = &hw->phy;
2096 if (!hw->phy.ops.read_reg)
2099 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2105 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2114 if (phy->smart_speed == e1000_smart_speed_on) {
2115 ret_val = phy->ops.read_reg(hw,
2122 ret_val = phy->ops.write_reg(hw,
2127 } else if (phy->smart_speed == e1000_smart_speed_off) {
2128 ret_val = phy->ops.read_reg(hw,
2135 ret_val = phy->ops.write_reg(hw,
2141 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2142 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2143 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2145 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2151 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2157 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2170 * A downshift is detected by querying the PHY link health.
2174 struct e1000_phy_info *phy = &hw->phy;
2180 switch (phy->type) {
2197 phy->speed_downgraded = false;
2201 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2204 phy->speed_downgraded = !!(phy_data & mask);
2215 * Polarity is determined based on the PHY specific status register.
2219 struct e1000_phy_info *phy = &hw->phy;
2225 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2228 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2241 * Polarity is determined based on the PHY port status register, and the
2246 struct e1000_phy_info *phy = &hw->phy;
2255 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2271 ret_val = phy->ops.read_reg(hw, offset, &data);
2274 phy->cable_polarity = ((data & mask)
2282 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2289 struct e1000_phy_info *phy = &hw->phy;
2297 if (phy->polarity_correction) {
2305 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2308 phy->cable_polarity = ((phy_data & mask)
2329 if (!hw->phy.ops.read_reg)
2334 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2337 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2352 * e1000_phy_has_link_generic - Polls PHY for link
2358 * Polls the PHY status register for link, 'iterations' number of times.
2368 if (!hw->phy.ops.read_reg)
2376 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2387 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2404 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2407 * Reads the PHY specific status register to retrieve the cable length
2409 * maximum values to get the "average" cable length. The m88 PHY has four
2420 struct e1000_phy_info *phy = &hw->phy;
2426 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2436 phy->min_cable_length = e1000_m88_cable_length_table[index];
2437 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2439 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2446 struct e1000_phy_info *phy = &hw->phy;
2453 switch (hw->phy.id) {
2455 /* Get cable length from PHY Cable Diagnostics Control Reg */
2456 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2457 (I347AT4_PCDL + phy->addr),
2463 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2470 /* Populate the phy structure with cable length in meters */
2471 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2472 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2473 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2480 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2485 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2489 /* Get cable length from PHY Cable Diagnostics Control Reg */
2490 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2496 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2502 /* Populate the phy structure with cable length in meters */
2503 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2504 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2505 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2508 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2516 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2521 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2525 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2536 phy->min_cable_length = e1000_m88_cable_length_table[index];
2537 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2539 phy->cable_length = (phy->min_cable_length +
2540 phy->max_cable_length) / 2;
2543 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2557 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2569 struct e1000_phy_info *phy = &hw->phy;
2585 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2618 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2620 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2622 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2628 * e1000_get_phy_info_m88 - Retrieve PHY information
2631 * Valid for only copper links. Read the PHY status register (sticky read)
2632 * to verify that link is up. Read the PHY special control register to
2633 * determine the polarity and 10base-T extended distance. Read the PHY
2639 struct e1000_phy_info *phy = &hw->phy;
2646 if (phy->media_type != e1000_media_type_copper) {
2647 DEBUGOUT("Phy info is only valid for copper media\n");
2656 DEBUGOUT("Phy info is only valid if link is up\n");
2660 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2664 phy->polarity_correction = !!(phy_data &
2671 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2675 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2678 ret_val = hw->phy.ops.get_cable_length(hw);
2682 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2686 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2690 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2695 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2696 phy->local_rx = e1000_1000t_rx_status_undefined;
2697 phy->remote_rx = e1000_1000t_rx_status_undefined;
2704 * e1000_get_phy_info_igp - Retrieve igp PHY information
2707 * Read PHY status to determine if link is up. If link is up, then
2709 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2714 struct e1000_phy_info *phy = &hw->phy;
2726 DEBUGOUT("Phy info is only valid if link is up\n");
2730 phy->polarity_correction = true;
2736 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2740 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2744 ret_val = phy->ops.get_cable_length(hw);
2748 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2752 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2756 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2760 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2761 phy->local_rx = e1000_1000t_rx_status_undefined;
2762 phy->remote_rx = e1000_1000t_rx_status_undefined;
2769 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2772 * Populates "phy" structure with various feature states.
2776 struct e1000_phy_info *phy = &hw->phy;
2788 DEBUGOUT("Phy info is only valid if link is up\n");
2792 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2795 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2797 if (phy->polarity_correction) {
2803 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2808 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2812 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2815 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2816 phy->local_rx = e1000_1000t_rx_status_undefined;
2817 phy->remote_rx = e1000_1000t_rx_status_undefined;
2823 * e1000_phy_sw_reset_generic - PHY software reset
2826 * Does a software reset of the PHY by reading the PHY control register and
2827 * setting/write the control register reset bit to the PHY.
2836 if (!hw->phy.ops.read_reg)
2839 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2844 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2854 * e1000_phy_hw_reset_generic - PHY hardware reset
2859 * bit in the PHY. Wait the appropriate delay time for the device to
2864 struct e1000_phy_info *phy = &hw->phy;
2870 if (phy->ops.check_reset_block) {
2871 ret_val = phy->ops.check_reset_block(hw);
2876 ret_val = phy->ops.acquire(hw);
2884 usec_delay(phy->reset_delay_us);
2891 phy->ops.release(hw);
2893 return phy->ops.get_cfg_done(hw);
2913 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2920 DEBUGOUT("Running IGP 3 PHY init script\n");
2922 /* PHY init IGP 3 */
2924 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2926 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2928 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2930 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2932 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2934 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2936 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2938 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2940 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2942 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2943 /* Force 1000 ( required for enabling PHY regs configuration) */
2944 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2946 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2948 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2950 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2952 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2954 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2956 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2958 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2960 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2962 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2964 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2966 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2968 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2970 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2972 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2974 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2978 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2980 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2984 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2986 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2988 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2990 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2996 * e1000_get_phy_type_from_id - Get PHY type from id
2997 * @phy_id: phy_id read from the phy
2999 * Returns the phy type from the id.
3061 * e1000_determine_phy_address - Determines PHY address.
3064 * This uses a trial and error method to loop through possible PHY
3065 * addresses. It tests each by reading the PHY ID registers and
3074 hw->phy.id = phy_type;
3077 hw->phy.addr = phy_addr;
3082 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3085 * PHY address
3099 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3103 * Returns the phy address for the page requested.
3116 * e1000_write_phy_reg_bm - Write BM PHY register
3121 * Acquires semaphore, if necessary, then writes the data to PHY register
3131 ret_val = hw->phy.ops.acquire(hw);
3142 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3147 /* Page select is register 31 for phy address 1 and 22 for
3148 * phy address 2 and 3. Page select is shifted only for
3149 * phy address 1.
3151 if (hw->phy.addr == 1) {
3159 /* Page is shifted left, PHY expects (page x 32) */
3170 hw->phy.ops.release(hw);
3175 * e1000_read_phy_reg_bm - Read BM PHY register
3180 * Acquires semaphore, if necessary, then reads the PHY register at offset
3191 ret_val = hw->phy.ops.acquire(hw);
3202 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3207 /* Page select is register 31 for phy address 1 and 22 for
3208 * phy address 2 and 3. Page select is shifted only for
3209 * phy address 1.
3211 if (hw->phy.addr == 1) {
3219 /* Page is shifted left, PHY expects (page x 32) */
3229 hw->phy.ops.release(hw);
3234 * e1000_read_phy_reg_bm2 - Read BM PHY register
3239 * Acquires semaphore, if necessary, then reads the PHY register at offset
3250 ret_val = hw->phy.ops.acquire(hw);
3261 hw->phy.addr = 1;
3264 /* Page is shifted left, PHY expects (page x 32) */
3275 hw->phy.ops.release(hw);
3280 * e1000_write_phy_reg_bm2 - Write BM PHY register
3285 * Acquires semaphore, if necessary, then writes the data to PHY register
3295 ret_val = hw->phy.ops.acquire(hw);
3306 hw->phy.addr = 1;
3309 /* Page is shifted left, PHY expects (page x 32) */
3321 hw->phy.ops.release(hw);
3343 /* All page select, port ctrl and wakeup registers use phy address 1 */
3344 hw->phy.addr = 1;
3355 DEBUGOUT2("Could not read PHY register %d.%d\n",
3360 /* Enable both PHY wakeup mode and Wakeup register page writes.
3361 * Prevent a power state change by disabling ME and Host PHY wakeup.
3369 DEBUGOUT2("Could not write PHY register %d.%d\n",
3410 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3417 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3424 * Read the PHY register at offset and store the retrieved information in
3425 * data, or write data to PHY register at offset. Note the procedure to
3426 * access the PHY wakeup registers is different than reading the other PHY
3438 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3458 /* Enable access to PHY wakeup registers */
3461 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3466 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3486 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3497 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3500 * In the case of a PHY power down to save power, or to turn off link during a
3508 /* The PHY will retain its settings across a power down/up cycle */
3509 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3511 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3515 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3518 * In the case of a PHY power down to save power, or to turn off link during a
3526 /* The PHY will retain its settings across a power down/up cycle */
3527 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3529 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3534 * __e1000_read_phy_reg_hv - Read HV PHY register
3541 * Acquires semaphore, if necessary, then reads the PHY register at offset
3551 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3556 ret_val = hw->phy.ops.acquire(hw);
3578 /* Page is shifted left, PHY expects (page x 32) */
3582 hw->phy.addr = phy_addr;
3589 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3596 hw->phy.ops.release(hw);
3602 * e1000_read_phy_reg_hv - Read HV PHY register
3607 * Acquires semaphore then reads the PHY register at offset and stores
3617 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3622 * Reads the PHY register at offset and stores the retrieved information
3631 * e1000_read_phy_reg_page_hv - Read HV PHY register
3636 * Reads the PHY register at offset and stores the retrieved information
3645 * __e1000_write_phy_reg_hv - Write HV PHY register
3652 * Acquires semaphore, if necessary, then writes the data to PHY register
3661 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3666 ret_val = hw->phy.ops.acquire(hw);
3688 * Power Down (when bit 11 of the PHY Control register is set)
3690 if ((hw->phy.type == e1000_phy_82578) &&
3691 (hw->phy.revision >= 1) &&
3692 (hw->phy.addr == 2) &&
3704 /* Page is shifted left, PHY expects (page x 32) */
3708 hw->phy.addr = phy_addr;
3715 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3723 hw->phy.ops.release(hw);
3729 * e1000_write_phy_reg_hv - Write HV PHY register
3734 * Acquires semaphore then writes the data to PHY register at the offset.
3743 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3748 * Writes the data to PHY register at the offset. Assumes semaphore
3757 * e1000_write_phy_reg_page_hv - Write HV PHY register
3762 * Writes the data to PHY register at the offset. Assumes semaphore
3771 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3785 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3791 * Reads the PHY register at offset and stores the retreived information
3794 * These accesses done with PHY address 2 and without using pages.
3805 /* This takes care of the difference with desktop vs mobile phy */
3806 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3810 /* All operations in this function are phy address 2 */
3811 hw->phy.addr = 2;
3837 * a link up indication before the PHY does. If small packets are sent
3839 * being properly accounted for by the PHY and will stall preventing
3841 * packet buffer after the PHY detects link up.
3850 if (hw->phy.type != e1000_phy_82578)
3853 /* Do not apply workaround if in PHY loopback bit 14 set */
3854 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3859 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3873 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3879 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3889 * Polarity is determined based on the PHY specific status register.
3893 struct e1000_phy_info *phy = &hw->phy;
3899 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3902 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3910 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3913 * Calls the PHY setup function to force speed and duplex.
3917 struct e1000_phy_info *phy = &hw->phy;
3924 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3930 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3936 if (phy->autoneg_wait_to_complete) {
3937 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3956 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3959 * Read PHY status to determine if link is up. If link is up, then
3961 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3966 struct e1000_phy_info *phy = &hw->phy;
3978 DEBUGOUT("Phy info is only valid if link is up\n");
3982 phy->polarity_correction = true;
3988 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3992 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3996 ret_val = hw->phy.ops.get_cable_length(hw);
4000 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4004 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
4008 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
4012 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
4013 phy->local_rx = e1000_1000t_rx_status_undefined;
4014 phy->remote_rx = e1000_1000t_rx_status_undefined;
4021 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
4029 struct e1000_phy_info *phy = &hw->phy;
4035 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4045 phy->cable_length = length;
4051 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4056 * Acquires semaphore, if necessary, then writes the data to PHY register
4067 ret_val = hw->phy.ops.acquire(hw);
4077 hw->phy.ops.release(hw);
4082 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4088 * Acquires semaphore, if necessary, then reads the data in the PHY register
4099 ret_val = hw->phy.ops.acquire(hw);
4109 hw->phy.ops.release(hw);
4119 * Reads the mPHY control register in the PHY at offset and stores the
4263 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");
4283 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
4287 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
4291 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
4297 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
4299 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
4304 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);