| /freebsd-src/sys/contrib/device-tree/Bindings/phy/ |
| H A D | phy-hi3798cv200-combphy.txt | 1 HiSilicon STB PCIE/SATA/USB3 PHY
4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
19 - hisilicon,mode-select-bits: If the phy device support mode select,
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| H A D | phy-miphy28lp.txt | 1 STMicroelectronics STi MIPHY28LP PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
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| /freebsd-src/sys/contrib/device-tree/Bindings/net/ |
| H A D | micrel.txt | 1 Micrel PHY properties.
7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
21 See the respective PHY datasheet for the mode values.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
29 Note that this option in only needed for certain PHY revisions with a
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
32 actually select a mode.
34 - clocks, clock-names: contains clocks according to the common clock bindings.
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| H A D | allwinner,sun4i-a10-mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun4i-a10-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 - $ref: mdio.yaml#
16 # Select every compatible, including the deprecated ones. This way, we
18 # we will validate the node thanks to the select, but won't report it
20 select:
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| H A D | stm32-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schema
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| H A D | icplus-ip101ag.txt | 3 There are different models of the IP101G Ethernet PHY:
4 - IP101GR (32-pin QFN package)
5 - IP101G (die only, no package)
6 - IP101GA (48-pin LQFP package)
8 There are different models of the IP101A Ethernet PHY (which is the
10 - IP101A (48-pin LQFP package)
11 - IP101AH (48-pin LQFP package)
13 Optional properties for the IP101GR (32-pin QFN package):
15 - icplus,select-rx-error:
17 interrupts are not routed outside the PHY in this mode.
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| H A D | sff,sfp.txt | 1 Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
6 - compatible : must be one of
10 - i2c-bus : phandle of an I2C bus controller for the SFP two wire serial
15 - mod-def0-gpios : GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS)
19 - los-gpios : GPIO phandle and a specifier of the Receiver Loss of Signal
22 - tx-fault-gpios : GPIO phandle and a specifier of the Module Transmitter
25 - tx-disable-gpios : GPIO phandle and a specifier of the Transmitter Disable
28 - rate-select0-gpios : GPIO phandle and a specifier of the Rx Signaling Rate
29 Select (AKA RS0) output gpio signal, low: low Rx rate, high: high Rx rate
32 - rate-select1-gpios : GPIO phandle and a specifier of the Tx Signaling Rate
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| H A D | sff,sfp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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| H A D | amlogic,meson-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schema
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| H A D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Commo
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| H A D | rockchip-dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/rockchip-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Wu <david.wu@rock-chip
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| /freebsd-src/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | ti,j721e-system-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@ti.com>
23 - Roger Quadros <rogerq@kernel.org>
28 - enum:
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| /freebsd-src/sys/contrib/alpine-hal/ |
| H A D | al_hal_serdes_25g_regs.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
132 /* Bit-wise write enable */
138 * 0x0 – Select reference clock from Bump
139 * 0x1 – Select inter-macro reference clock from the left side
141 * 0x3 – Select inter-macro reference clock from the right side
155 * 0x1 – Select reference clock from Bump
156 * 0x2 – Select inter-macro reference clock input from right side
171 * 0x1 – Select reference clock from Bump
172 * 0x2 – Select inter-macro reference clock input from left side
186 * Program memory acknowledge - Only when the access
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| /freebsd-src/sys/dev/mii/ |
| H A D | nsphyterreg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
40 * PHY register definitions here, since the two are, for our purposes,
44 #define MII_NSPHYTER_PHYSTS 0x10 /* PHY status */
65 #define PHYSTS_MP_DESCRLK 0x0200 /* de-scrambler lock */
72 #define MII_NSPHYTER_MIPSCR 0x11 /* MII interrupt PHY specific
78 #define MII_NSPHYTER_MIPGSR 0x12 /* MII interrupt PHY generic
85 #define MIPGSR_MSK_ANC 0x0800 /* mask auto-neg complete event */
96 #define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */
140 #define BTSCR_LS_SEL 0x0040 /* low squelch select */
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| H A D | brgphyreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
52 #define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
87 #define BRGPHY_ANER_NP 0x0004 /* Local PHY can next page */
113 #define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
114 #define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
115 #define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
116 #define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
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| H A D | e1000phy.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
41 * 1000baseSX PHY.
43 * Jung-uk Kim <jkim@niksun.com>
140 (sc->mii_flags & MIIF_MACPRIV0) != 0) in e1000phy_attach()
141 sc->mii_flags |= MIIF_PHYPRIV0; in e1000phy_attach()
143 switch (sc->mii_mpd_model) { in e1000phy_attach()
147 sc->mii_flags |= MIIF_HAVEFIBER; in e1000phy_attach()
152 * Some 88E1149 PHY's page select is initialized to in e1000phy_attach()
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| H A D | rgephyreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
44 * RealTek 8169S/8110S gigE PHY registers
50 #define RGEPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
57 #define RGEPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
109 #define RGEPHY_ANER_NP 0x0004 /* Local PHY can next page */
120 #define RGEPHY_1000CTL_MSC 0x0800 /* Master/Slave select */
140 #define RGEPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
141 #define RGEPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
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| /freebsd-src/sys/contrib/device-tree/Bindings/soc/samsung/ |
| H A D | exynos-pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
12 # Custom select to avoid matching all nodes with 'syscon'
13 select:
18 - google,gs101-pmu
19 - samsung,exynos3250-pmu
20 - samsung,exynos4210-pmu
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| /freebsd-src/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_an_lt_wrapper_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
152 * Default Auto-Negotiation Enable. If ‘1’, the auto-negotiation process will
153 * start after reset de-assertion. The application can also start the
154 * auto-negotiation process by writing the KXAN_CONTROL.an_enable bit with ‘1’.
175 * PHY LOS indication selection
176 * 0 - Select input from the SerDes
177 * 1 - Select register value from phy_los_in_def
180 /* PHY LOS default value */
182 /* PHY LOS polarity */
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| /freebsd-src/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | marvell,xenon-sdhci.txt | 7 clock and PHY.
11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-ap807-sdhci": For controllers on Armada AP807.
16 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
18 - clocks:
23 - clock-names:
28 - reg:
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| /freebsd-src/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | armada-xp-lenovo-ix4-300d.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for Lenovo Iomega ix4-300d
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "armada-xp-mv78230.dtsi"
15 model = "Lenovo Iomega ix4-300d";
16 compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230",
17 "marvell,armadaxp", "marvell,armada-370-xp";
20 stdout-path = "serial0:115200n8";
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| H A D | armada-375-db.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-88F6720)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include "armada-375.dtsi"
18 compatible = "marvell,a375-db", "marvell,armada375";
21 stdout-path = "serial0:115200n8";
57 pinctrl-0 = <&spi0_pins>;
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| /freebsd-src/sys/dev/usb/net/ |
| H A D | if_udav.c | 3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
17 * 3. Neither the name of the author nor the names of any co-contributors
36 * DM9601(DAVICOM USB to Ethernet MAC Controller with Integrated 10/100 PHY)
38 * http://ptm2.cc.utu.fi/ftp/network/cards/DM9601/From_NET/DM9601-DS-P01-930914.pdf
175 /* Corega USB-TXC */
239 udav_csr_read(sc, UDAV_PAR, ue->ue_eaddr, ETHER_ADDR_LEN); in udav_attach_post()
247 if (uaa->usb_mode != USB_MODE_HOST) in udav_probe()
249 if (uaa->info.bConfigIndex != UDAV_CONFIG_INDEX) in udav_probe()
251 if (uaa->info.bIfaceIndex != UDAV_IFACE_INDEX) in udav_probe()
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| /freebsd-src/sys/dev/igc/ |
| H A D | igc_phy.h | 1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
48 #define IGP01IGC_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
50 #define IGP01IGC_PHY_PAGE_SELECT 0x1F /* Page Select */
51 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
54 #define IGC_I225_PHPM 0x0E14 /* I225 PHY Power Management */
60 #define IGC_I225_PHPM_RST_COMPL 0x0100 /* PHY Reset Completed */
62 #define IGC_I225_PHPM_ULP 0x0400 /* Ultra Low-Power Mode */
65 /* GPY211 - I225 defines */
110 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */
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| /freebsd-src/sys/contrib/device-tree/Bindings/pci/ |
| H A D | amlogic,axg-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/amlogic,axg-pci
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