Lines Matching +full:phy +full:- +full:select
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
52 #define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
87 #define BRGPHY_ANER_NP 0x0004 /* Local PHY can next page */
113 #define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
114 #define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
115 #define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
116 #define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
118 #define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */
119 #define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */
124 #define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */
136 #define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */
164 #define BRGPHY_MII_EPHY_PTEST 0x17 /* 5906 PHY register */
220 #define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */
221 #define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */
266 /* Begin: Shared SerDes PHY register definitions */
287 /* End: Shared SerDes PHY register definitions */
291 /* Begin: PHY register values for the 5706 PHY */
295 * Aux control shadow register, bits 0-2 select function (0x00 to
307 * bits 14-10 select function (0x00 to 0x1F).
314 /* Shadow 0x1C Clock Alignment Control Register (select value 0x03) */
318 /* Shadow 0x1C Mode Control Register (select value 0x1F) */
320 /* When set, Regs 0-0x0F are 1000X, else 1000T */
330 /* End: PHY register values for the 5706 PHY */
334 /* Begin: PHY register values for the 5708S SerDes PHY */
341 /* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */
374 /* End: PHY register values for the 5708S SerDes PHY */
378 /* Begin: PHY register values for the 5709S SerDes PHY */
404 /* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */
429 /* End: PHY register values for the 5709S SerDes PHY */