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/freebsd-src/sys/dts/arm/
H A Dannapurna-alpine.dts1 /*-
28 /dts-v1/;
32 #address-cells = <1>;
33 #size-cells = <1>;
40 #address-cells = <1>;
41 #size-cells = <0>;
45 compatible = "arm,cortex-a15";
47 d-cache-line-size = <64>; // 64 bytes
48 i-cache-line-size = <64>; // 64 bytes
49 d-cache-size = <0x8000>; // L1, 32K
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/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls2080a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57-pm
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H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gi
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H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controlle
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/freebsd-src/sys/contrib/device-tree/Bindings/pci/
H A Dv3-v360epc-pci.txt6 - compatible: should be one of:
7 "v3,v360epc-pci"
8 "arm,integrator-ap-pci", "v3,v360epc-pci"
9 - reg: should contain two register areas:
12 - interrupts: should contain a reference to the V3 error interrupt
14 - bus-range: see pci.txt
15 - ranges: this follows the standard PCI bindings in the IEEE Std
16 1275-1994 (see pci.txt) with the following restriction:
17 - The non-prefetchable and prefetchable memory windows must
19 - The prefetchable memory window must be immediately adjacent
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H A Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
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H A Dnvidia,tegra194-pcie.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml and
5 snps,dw-pcie-ep.yaml.
10 - power-domains: A phandle to the node that controls power to the respective
20 "include/dt-bindings/power/tegra194-powergate.h" file.
21 - reg: A list of physical base address and length pairs for each set of
22 controller registers. Must contain an entry for each entry in the reg-names
24 - reg-names: Must include the following entries:
26 "config": As per the definition in snps,dw-pcie.yaml
32 - interrupts: A list of interrupt outputs of the controller. Must contain an
33 entry for each entry in the interrupt-names property.
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H A Dversatile.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dxilinx-nwl-pcie.txt4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
21 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
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H A Dfaraday,ftpci100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dfaraday,ftpci100.txt14 - compatible: ranging from specific to generic, should be one of
15 "cortina,gemini-pci", "faraday,ftpci100"
16 "cortina,gemini-pci-dual", "faraday,ftpci100-dual"
18 "faraday,ftpci100-dual"
19 - reg: memory base and size for the host bridge
20 - #address-cells: set to <3>
21 - #size-cells: set to <2>
22 - #interrupt-cells: set to <1>
23 - bus-range: set to <0x00 0xff>
24 - device_type, set to "pci"
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H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generi
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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H A Dpci-armada8k.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "marvell,armada8k-pcie"
8 - reg: must contain two register regions
9 - the control register region
10 - the config space region
11 - reg-names:
12 - "ctrl" for the control register region
13 - "config" for the config space region
14 - interrupts: Interrupt specifier for the PCIe controller
15 - clocks: reference to the PCIe controller clocks
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H A Dlayerscape-pci.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
22 "fsl,ls1043a-pcie"
23 "fsl,ls1012a-pcie"
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H A Daxis,artpec6-pcie.txt1 * Axis ARTPEC-6 PCIe interface
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
13 - reg-names: Must include the following entries:
14 - "dbi"
15 - "phy"
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H A Duniphier-pcie.txt9 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
12 - compatible: Should be "socionext,uniphier-pcie".
13 - reg: Specifies offset and length of the register set for the device.
14 According to the reg-names, appropriate register sets are required.
15 - reg-names: Must include the following entries:
16 "dbi" - controller configuration registers
17 "link" - SoC-specific glue layer registers
18 "config" - PCIe configuration space
19 "atu" - iATU registers for DWC version 4.80 or later
20 - clocks: A phandle to the clock gate for PCIe glue layer including
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/freebsd-src/sys/contrib/device-tree/src/arm/st/
H A Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
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H A Dspear1340.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
16 compatible = "st,spear-spics-gpio";
18 st-spics,peripcfg-reg = <0x42c>;
19 st-spics,sw-enable-bit = <21>;
20 st-spics,cs-value-bit = <20>;
21 st-spics,cs-enable-mask = <3>;
22 st-spics,cs-enable-shift = <18>;
23 gpio-controller;
24 #gpio-cells = <2>;
29 compatible = "st,spear1340-miphy";
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/freebsd-src/sys/contrib/device-tree/src/arm/arm/
H A Dversatile-pb.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "versatile-ab.dts"
6 compatible = "arm,versatile-pb";
10 sic: interrupt-controller@10003000 {
11 clear-mask = <0xffffffff>;
14 * figure 3-30 page 3-74 of ARM DUI 0224B
16 valid-mask = <0x7fe003ff>;
23 gpio-controller;
24 #gpio-cells = <2>;
25 interrupt-controller;
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/freebsd-src/usr.sbin/pciconf/
H A Dpciconf.853 normally only the super-user.
60 .Bd -literal
80 hex digits, followed by the sub-class and the interface bytes.
99 .Em multi-function
115 .Bd -literal
122 All fields retain the same definition as with the non-compact form.
143 .Bd -literal
144 window[1c] = type I/O Port, range 16, addr 0x5000-0x8fff, enabled
153 .Dq Prefetchable Memory ,
168 .Bd -literal
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H A Dcap.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
16 * 3. Neither the name of the author nor the names of any co-contributors
55 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); in cap_power()
56 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); in cap_power()
69 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4); in cap_agp()
70 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4); in cap_agp()
131 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2); in cap_msi()
150 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4); in cap_pcix()
151 printf("PCI-X "); in cap_pcix()
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/freebsd-src/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gi
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/freebsd-src/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-therma
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/freebsd-src/sys/contrib/device-tree/src/arm/amazon/
H A Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
57 clock-frequency = <1700000000>;
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