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Searched +full:kpss +full:- +full:acc (Results 1 – 15 of 15) sorted by relevance

/freebsd-src/sys/contrib/device-tree/Bindings/power/
H A Dqcom,kpss-acc-v2.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/power/qcom,kpss-acc-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v2
10 - Christian Marangi <ansuelsmth@gmail.com>
13 The KPSS ACC provides clock, power manager, and reset control to a Krait CPU.
14 There is one ACC register region per CPU within the KPSS remapped region as
15 well as an alias register region that remaps accesses to the ACC associated
16 with the CPU accessing the region. ACC v2 is currently used as a
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/freebsd-src/sys/contrib/device-tree/Bindings/arm/msm/
H A Dqcom,kpss-acc.txt1 Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
3 The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
4 There is one ACC register region per CPU within the KPSS remapped region as
5 well as an alias register region that remaps accesses to the ACC associated
10 - compatible:
14 "qcom,kpss-acc-v1"
15 "qcom,kpss-acc-v2"
17 - reg:
19 Value type: <prop-encoded-array>
24 - clocks:
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/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,kpss-acc-v1.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
10 - Christian Marangi <ansuelsmth@gmail.com>
13 The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
14 There is one ACC register region per CPU within the KPSS remapped region as
15 well as an alias register region that remaps accesses to the ACC associated
16 with the CPU accessing the region. ACC v1 is currently used as a
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-msm8960.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-binding
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H A Dqcom-ipq4019.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gi
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H A Dqcom-apq8084.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-binding
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H A Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm896
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H A Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-binding
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H A Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm897
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/freebsd-src/sys/contrib/device-tree/Bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bi
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/freebsd-src/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,spm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
20 - enum:
21 - qcom,sdm660-gold-saw2-v4.1-l2
22 - qcom,sdm660-silver-saw2-v4.1-l2
23 - qcom,msm8998-gold-saw2-v4.1-l2
24 - qcom,msm8998-silver-saw2-v4.1-l2
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/freebsd-src/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8939.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-binding
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H A Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm891
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H A Dqcs404.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
8 #include <dt-bindings/clock/qcom,turingcc-qcs40
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/freebsd-src/sys/arm/qualcomm/
H A Dipq4018_mp.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
70 mp_maxid = ncpu - 1; in ipq4018_mp_setmaxid()
81 * "qcom,kpss-acc-v2". If this path gets turned into in ipq4018_start_ap()
84 * switch based on "enable-method". in ipq4018_start_ap()
95 * First step - SCM call to set the cold boot address to mpentry, so in ipq4018_mp_start_ap()
104 * Next step - loop over the CPU nodes and do the per-CPU setup in ipq4018_mp_start_ap()