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/freebsd-src/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-ocores.txt1 Device tree configuration for i2c-ocores
4 - compatible : "opencores,i2c-ocores"
6 "sifive,fu540-c000-i2c", "sifive,i2c0"
7 For Opencore based I2C IP block reimplemented in
8 FU540-C000 SoC.
9 "sifive,fu740-c000-i2c", "sifive,i2c0"
10 For Opencore based I2C IP block reimplemented in
11 FU740-C000 SoC.
12 Please refer to sifive-blocks-ip-versioning.txt for
14 - reg : bus address start and address range size of device
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H A Dopencores,i2c-ocores.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
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H A Dmicrochip,corei2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
20 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
21 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
32 clock-frequency:
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H A Di2c-demux-pinctrl.txt1 Pinctrl-based I2C Bus DeMux
5 the pinctrl device tree bindings. This may be used to select one I2C IP core at
7 IP core on the SoC. The most simple example is to fall back to GPIO bitbanging
8 if your current runtime configuration hits an errata of the internal IP core.
10 +-------------------------------+
12 | | +-----+ +-----+
13 | +------------+ | | dev | | dev |
14 | |I2C IP Core1|--\ | +-----+ +-----+
15 | +------------+ \-------+ | | |
16 | |Pinctrl|--|------+--------+
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H A Di2c-demux-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-demu
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/freebsd-src/sys/contrib/device-tree/Bindings/mmc/
H A Drenesas,sdhi.txt4 - compatible: should contain one or more of the following:
5 "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
6 "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
7 "renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC
8 "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
9 "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
10 "renesas,sdhi-r8a7742" - SDHI IP on R8A7742 SoC
11 "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
12 "renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC
13 "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
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/freebsd-src/sys/contrib/device-tree/Bindings/media/
H A Dnxp,imx-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
15 receiver IP core named CSIS. The IP core originates from Samsung, and may be
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H A Dnxp,imx7-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
15 receiver IP core named CSIS. The IP core originates from Samsung, and may be
[all …]
H A Dsamsung-fimc.txt2 ----------------------------------------------
4 The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
6 the S5P SoCs series known as CAMIF), MIPI CSIS, FIMC-LITE and FIMC-IS (ISP).
8 The sub-subdevices are defined as child nodes of the common 'camera' node which
10 any single sub-device, like common camera port pins or the CAMCLK clock outputs
14 --------------------
18 - compatible: must be "samsung,fimc", "simple-bus"
19 - clocks: list of clock specifiers, corresponding to entries in
20 the clock-names property;
21 - clock-names : must contain "sclk_cam0", "sclk_cam1", "pxl_async0",
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H A Dsamsung,exynos4210-fimc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,exynos4210-fim
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H A Dsamsung-mipi-csis.txt1 Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS)
2 -------------------------------------------------------------
6 - compatible : "samsung,s5pv210-csis" for S5PV210 (S5PC110),
7 "samsung,exynos4210-csis" for Exynos4210 (S5PC210),
8 "samsung,exynos4212-csis" for Exynos4212/Exynos4412,
9 "samsung,exynos5250-csis" for Exynos5250;
10 - reg : offset and length of the register set for the device;
11 - interrupts : should contain MIPI CSIS interrupt; the format of the
13 - bus-width : maximum number of data lanes supported (SoC specific);
14 - vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V);
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H A Dimx7-mipi-csi2.txt5 --------------
7 This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
8 compatible with previous version of Samsung D-phy.
12 - compatible : "fsl,imx7-mipi-csi2";
13 - reg : base address and length of the register set for the device;
14 - interrupts : should contain MIPI CSIS interrupt;
15 - clocks : list of clock specifiers, see
16 Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
17 - clock-names : must contain "pclk", "wrap" and "phy" entries, matching
18 entries in the clock property;
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/freebsd-src/sys/contrib/device-tree/Bindings/
H A Dxilinx.txt1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10 Each IP-core has a set of parameters which the FPGA designer can use to
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
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/freebsd-src/sys/contrib/device-tree/Bindings/clock/ti/
H A Ddra7-atl.txt1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
16 Since the clock instances are part of a single IP this binding is used as a node
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/freebsd-src/sys/contrib/device-tree/src/arc/
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cell
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/freebsd-src/sys/contrib/device-tree/Bindings/net/can/
H A Dmpc5xxx-mscan.txt2 ------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
7 fsl,mpc5200-mscan nodes
8 -----------------------
9 In addition to the required compatible-, reg- and interrupt-properties, you can
10 also specify which clock source shall be used for the controller:
12 - fsl,mscan-clock-source : a string describing the clock source. Valid values
13 are: "ip" for ip bus clock
14 "ref" for reference clock (XTAL)
18 fsl,mpc5121-mscan nodes
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H A Dgrcan.txt3 The GRCAN and CRHCAN CAN controllers are available in the GRLIB VHDL IP core
12 - name : Should be "GAISLER_GRCAN", "01_03d", "GAISLER_GRHCAN" or "01_034"
14 - reg : Address and length of the register set for the device
16 - freq : Frequency of the external oscillator clock in Hz (the frequency of
19 - interrupts : Interrupt number for this device
23 - systemid : If not present or if the value of the least significant 16 bits
24 of this 32-bit property is smaller than GRCAN_TXBUG_SAFE_GRLIB_VERSION
27 For further information look in the documentation for the GLIB IP core library:
/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dst,stm32-rcc.txt1 STMicroelectronics STM32 Reset and Clock Controller
4 The RCC IP is both a reset and a clock controller.
6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
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/freebsd-src/sys/contrib/device-tree/Bindings/clock/sifive/
H A Dfu540-prci.txt3 On the FU540 family of SoCs, most system-wide clock and reset integration
4 is via the PRCI IP block.
7 - compatible: Should be "sifive,<chip>-prci". Only one value is
8 supported: "sifive,fu540-c000-prci"
9 - reg: Should describe the PRCI's register target physical address region
10 - clocks: Should point to the hfclk device tree node and the rtcclk
11 device tree node. The RTC clock here is not a time-of-day clock,
12 but is instead a high-stability clock source for system timers
14 - #clock-cells: Should be <1>
16 The clock consumer should specify the desired clock via the clock ID
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/freebsd-src/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a779f0-spider-cpu.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
15 compatible = "renesas,spider-cpu", "renesas,r8a779f0";
29 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
30 stdout-path = "serial0:1843200n8";
34 compatible = "gpio-leds";
36 led-
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/freebsd-src/sys/contrib/device-tree/Bindings/display/bridge/
H A Dsamsung,mipi-dsim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
21 - enum:
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
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/freebsd-src/contrib/ntp/ntpq/
H A Dntpq.mdoc.in4 .\" EDIT THIS FILE WITH CAUTION (ntpq-opts.mdoc)
6 .\" It has been AutoGen-ed May 25, 2024 at 12:04:29 AM by AutoGen 5.18.16
7 .\" From the definitions ntpq-opts.def
8 .\" and the template file agmdoc-cmd.tpl
17 .Op Fl \-option\-name Ns Oo Oo Ns "=| " Oc Ns Ar value Oc
30 variables can be assembled, with raw and pretty\-printed output
106 .Bl -tag -width "help [command]" -compact -offset indent
142 be comma\-separated and not contain white space.
294 Association ids are used to identify system, peer and clock variables.
308 .Bl -tag -width "something" -compact -offset indent
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H A Dntpq.1ntpqmdoc4 .\" EDIT THIS FILE WITH CAUTION (ntpq-opts.mdoc)
6 .\" It has been AutoGen-ed May 25, 2024 at 12:04:29 AM by AutoGen 5.18.16
7 .\" From the definitions ntpq-opts.def
8 .\" and the template file agmdoc-cmd.tpl
17 .Op Fl \-option\-name Ns Oo Oo Ns "=| " Oc Ns Ar value Oc
30 variables can be assembled, with raw and pretty\-printed output
106 .Bl -tag -width "help [command]" -compact -offset indent
142 be comma\-separated and not contain white space.
294 Association ids are used to identify system, peer and clock variables.
308 .Bl -tag -width "something" -compact -offset indent
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/freebsd-src/usr.sbin/ntp/doc/
H A Dntpq.8
/freebsd-src/sys/contrib/device-tree/Bindings/ptp/
H A Dptp-qoriq.txt1 * Freescale QorIQ 1588 timer based PTP clock
5 - compatible Should be "fsl,etsec-ptp" for eTSEC
6 Should be "fsl,fman-ptp-timer" for DPAA FMan
7 Should be "fsl,dpaa2-ptp" for DPAA2
8 Should be "fsl,enetc-ptp" for ENETC
9 - reg Offset and length of the register set for the device
10 - interrupts There should be at least two interrupts. Some devices
13 Clock Properties:
15 - fsl,cksel Timer reference clock source.
16 - fsl,tclk-period Timer reference clock period in nanoseconds.
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