xref: /freebsd-src/sys/contrib/device-tree/Bindings/i2c/i2c-ocores.txt (revision 5def4c47d4bd90b209b9b4a4ba9faec15846d8fd)
1c66ec88fSEmmanuel VadotDevice tree configuration for i2c-ocores
2c66ec88fSEmmanuel Vadot
3c66ec88fSEmmanuel VadotRequired properties:
4c66ec88fSEmmanuel Vadot- compatible      : "opencores,i2c-ocores"
5c66ec88fSEmmanuel Vadot                    "aeroflexgaisler,i2cmst"
6c66ec88fSEmmanuel Vadot                    "sifive,fu540-c000-i2c", "sifive,i2c0"
7c66ec88fSEmmanuel Vadot                    For Opencore based I2C IP block reimplemented in
8*5def4c47SEmmanuel Vadot                    FU540-C000 SoC.
9*5def4c47SEmmanuel Vadot                    "sifive,fu740-c000-i2c", "sifive,i2c0"
10*5def4c47SEmmanuel Vadot                    For Opencore based I2C IP block reimplemented in
11*5def4c47SEmmanuel Vadot                    FU740-C000 SoC.
12*5def4c47SEmmanuel Vadot                    Please refer to sifive-blocks-ip-versioning.txt for
13*5def4c47SEmmanuel Vadot                    additional details.
14c66ec88fSEmmanuel Vadot- reg             : bus address start and address range size of device
15c66ec88fSEmmanuel Vadot- clocks          : handle to the controller clock; see the note below.
16c66ec88fSEmmanuel Vadot                    Mutually exclusive with opencores,ip-clock-frequency
17c66ec88fSEmmanuel Vadot- opencores,ip-clock-frequency: frequency of the controller clock in Hz;
18c66ec88fSEmmanuel Vadot                    see the note below. Mutually exclusive with clocks
19c66ec88fSEmmanuel Vadot- #address-cells  : should be <1>
20c66ec88fSEmmanuel Vadot- #size-cells     : should be <0>
21c66ec88fSEmmanuel Vadot
22c66ec88fSEmmanuel VadotOptional properties:
23c66ec88fSEmmanuel Vadot- interrupts      : interrupt number.
24c66ec88fSEmmanuel Vadot- clock-frequency : frequency of bus clock in Hz; see the note below.
25c66ec88fSEmmanuel Vadot                    Defaults to 100 KHz when the property is not specified
26c66ec88fSEmmanuel Vadot- reg-shift       : device register offsets are shifted by this value
27c66ec88fSEmmanuel Vadot- reg-io-width    : io register width in bytes (1, 2 or 4)
28c66ec88fSEmmanuel Vadot- regstep         : deprecated, use reg-shift above
29c66ec88fSEmmanuel Vadot
30c66ec88fSEmmanuel VadotNote
31c66ec88fSEmmanuel Vadotclock-frequency property is meant to control the bus frequency for i2c bus
32c66ec88fSEmmanuel Vadotdrivers, but it was incorrectly used to specify i2c controller input clock
33c66ec88fSEmmanuel Vadotfrequency. So the following rules are set to fix this situation:
34c66ec88fSEmmanuel Vadot- if clock-frequency is present and neither opencores,ip-clock-frequency nor
35c66ec88fSEmmanuel Vadot  clocks are, then clock-frequency specifies i2c controller clock frequency.
36c66ec88fSEmmanuel Vadot  This is to keep backwards compatibility with setups using old DTB. i2c bus
37c66ec88fSEmmanuel Vadot  frequency is fixed at 100 KHz.
38c66ec88fSEmmanuel Vadot- if clocks is present it specifies i2c controller clock. clock-frequency
39c66ec88fSEmmanuel Vadot  property specifies i2c bus frequency.
40c66ec88fSEmmanuel Vadot- if opencores,ip-clock-frequency is present it specifies i2c controller
41c66ec88fSEmmanuel Vadot  clock frequency. clock-frequency property specifies i2c bus frequency.
42c66ec88fSEmmanuel Vadot
43c66ec88fSEmmanuel VadotExamples:
44c66ec88fSEmmanuel Vadot
45c66ec88fSEmmanuel Vadot	i2c0: ocores@a0000000 {
46c66ec88fSEmmanuel Vadot		#address-cells = <1>;
47c66ec88fSEmmanuel Vadot		#size-cells = <0>;
48c66ec88fSEmmanuel Vadot		compatible = "opencores,i2c-ocores";
49c66ec88fSEmmanuel Vadot		reg = <0xa0000000 0x8>;
50c66ec88fSEmmanuel Vadot		interrupts = <10>;
51c66ec88fSEmmanuel Vadot		opencores,ip-clock-frequency = <20000000>;
52c66ec88fSEmmanuel Vadot
53c66ec88fSEmmanuel Vadot		reg-shift = <0>;	/* 8 bit registers */
54c66ec88fSEmmanuel Vadot		reg-io-width = <1>;	/* 8 bit read/write */
55c66ec88fSEmmanuel Vadot
56c66ec88fSEmmanuel Vadot		dummy@60 {
57c66ec88fSEmmanuel Vadot			compatible = "dummy";
58c66ec88fSEmmanuel Vadot			reg = <0x60>;
59c66ec88fSEmmanuel Vadot		};
60c66ec88fSEmmanuel Vadot	};
61c66ec88fSEmmanuel Vadotor
62c66ec88fSEmmanuel Vadot	i2c0: ocores@a0000000 {
63c66ec88fSEmmanuel Vadot		#address-cells = <1>;
64c66ec88fSEmmanuel Vadot		#size-cells = <0>;
65c66ec88fSEmmanuel Vadot		compatible = "opencores,i2c-ocores";
66c66ec88fSEmmanuel Vadot		reg = <0xa0000000 0x8>;
67c66ec88fSEmmanuel Vadot		interrupts = <10>;
68c66ec88fSEmmanuel Vadot		clocks = <&osc>;
69c66ec88fSEmmanuel Vadot		clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
70c66ec88fSEmmanuel Vadot
71c66ec88fSEmmanuel Vadot		reg-shift = <0>;	/* 8 bit registers */
72c66ec88fSEmmanuel Vadot		reg-io-width = <1>;	/* 8 bit read/write */
73c66ec88fSEmmanuel Vadot
74c66ec88fSEmmanuel Vadot		dummy@60 {
75c66ec88fSEmmanuel Vadot			compatible = "dummy";
76c66ec88fSEmmanuel Vadot			reg = <0x60>;
77c66ec88fSEmmanuel Vadot		};
78c66ec88fSEmmanuel Vadot	};
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