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/freebsd-src/contrib/llvm-project/clang/lib/Headers/
H A Df16cintrin.h1 /*===---- f16cintrin.h - F16C intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
23 /* NOTE: Intel documents the 128-bit versions of these as being in emmintrin.h,
28 /// Converts a 16-bit half-precision float value into a 32-bit float
36 /// A 16-bit half-precision float value.
37 /// \returns The converted 32-bit float value.
46 /// Converts a 32-bit single-precision float value to a 16-bit
47 /// half-precision float value.
58 /// A 32-bit single-precision float value to be converted to a 16-bit
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H A Davxneconvertintrin.h1 /*===-------------- avxneconvertintrin.h - AVXNECONVERT --------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
28 /// Convert scalar BF16 (16-bit) floating-point element
30 /// single-precision (32-bit) floating-point, broadcast it to packed
31 /// single-precision (32-bit) floating-point elements, and store the results in
43 /// A pointer to a 16-bit memory location. The address of the memory
46 /// A 128-bit vector of [4 x float].
61 /// Convert scalar BF16 (16-bit) floating-point element
63 /// single-precision (32-bit) floating-point, broadcast it to packed
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H A Dbmi2intrin.h1 /*===---- bmi2intrin.h - BMI2 intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
20 /// Copies the unsigned 32-bit integer \a __X and zeroes the upper bits
21 /// starting at bit number \a __Y.
36 /// The 32-bit source value to copy.
38 /// The lower 8 bits specify the bit number of the lowest bit to zero.
39 /// \returns The partially zeroed 32-bit value.
46 /// Deposit (scatter) low-order bits from the unsigned 32-bit integer \a __X
47 /// into the 32-bit result, according to the mask in the unsigned 32-bit
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H A Davx2intrin.h1 /*===---- avx2intrin.h - AVX2 intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
20 __target__("avx2,no-evex512"), __min_vector_width__(256)))
23 __target__("avx2,no-evex512"), __min_vector_width__(128)))
27 /// four unsigned 8-bit integers from the 256-bit integer vectors \a X and
30 /// Eight SAD results are computed using the lower half of the input
31 /// vectors, and another eight using the upper half. These 16-bit values
32 /// are returned in the lower and upper halves of the 256-bit result,
38 /// difference, and sums these four values to form one 16-bit result. The
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/freebsd-src/share/man/man4/
H A Dnge.416 .\" 4. Neither the name of the author nor the names of any co-contributors
42 .Bd -ragged -offset indent
50 .Bd -literal -offset indent
59 The DP83820 supports TBI (ten bit interface) and GMII
63 VLAN tagging/insertion as well as a 2048-bit multicast hash filter
68 full or half duplex.
81 .Bl -tag -width 10baseTXUTP
93 .Cm full-duplex
95 .Cm half-duplex
103 .Cm full-duplex
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H A Dmouse.43 .\" Kazutaka YOKOTA <yokota@zodiac.mech.utsunomiya-u.ac.jp>
54 Movement and button states are usually encoded in fixed-length data packets.
58 The mouse drivers may have ``non-blocking'' attribute which will make
74 .Bl -tag -width Byte_1 -compact
76 .Bl -tag -width bit_7 -compact
77 .It bit 7
79 .It bit 6..3
81 .It bit 2
83 .It bit 1
87 .It bit 0
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H A Dre.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
67 features, and use a descriptor-based DMA mechanism.
71 The 8139C+ is a single-chip solution combining both a 10/100 MAC and PHY.
73 The 816xS, 811xS, 8168 and 8111 are single-chip devices containing both a
76 in both 32-bit PCI and 64-bit PCI models.
78 embedded LAN-on-motherboard applications.
90 .Bl -tag -width ".Cm 10baseT/UTP"
102 .Cm full-duplex
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H A Dstge.440 .Bd -ragged -offset indent
48 .Bd -literal -offset indent
57 The Sundance/Tamarack TC9021 is found on the D-Link DGE-550T
59 It uses an external PHY or an external 10-bit interface.
65 receive interrupt moderation mechanism as well as a 64-bit
67 The Sundance/Tamarack TC9021 supports TBI (ten bit interface)
80 .Bl -tag -width ".Cm 10baseT/UTP"
92 .Cm full-duplex
94 .Cm half-duplex
102 .Cm full-duplex
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H A Dvge.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
59 The VT6120/VT6122 is a 33/66MHz 64-bit PCI device which combines a tri-speed
65 as well as VLAN filtering, a 64-entry CAM filter and a 64-entry VLAN filter,
66 64-bit multicast hash filter, 4 separate transmit DMA queues, flow control
93 .Bl -tag -width ".Cm 10baseT/UTP"
105 .Cm full-duplex
107 .Cm half-duplex
115 .Cm full-duplex
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H A Dsysmouse.41 .\" Copyright 1997 John-Mark Gurney. All rights reserved.
12 .\" THIS SOFTWARE IS PROVIDED BY John-Mark Gurney AND CONTRIBUTORS ``AS IS'' AND
72 .Bl -tag -width Byte_1 -compact
74 .Bl -tag -width bit_7 -compact
75 .It bit 7
77 .It bit 6..3
79 .It bit 2
81 .It bit 1
85 .It bit 0
89 The first half of horizontal movement count in two's complement;
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H A Dxl.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
57 and "tornado" bus-master Etherlink XL chips.
59 The Etherlink XL chips support built-in 10baseT, 10base2 and 10base5
63 NS 83840A 10/100 PHY for 10/100 Mbps support in full or half-duplex.
64 The 3c905B adapters have built-in autonegotiation logic mapped onto
67 adapters such as the 3c905-TX and 3c905B-TX are capable of 10 or
68 100Mbps data rates in either full or half duplex and can be manually
75 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
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H A Dmsk.435 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
56 features and an interrupt moderation mechanism as well as a 64-bit
58 The Yukon II supports TBI (ten bit interface) and GMII
71 .Bl -tag -width ".Cm 10baseT/UTP"
83 .Cm full-duplex
85 .Cm half-duplex
93 .Cm full-duplex
95 .Cm half-duplex
103 .Cm full-duplex
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H A Dbge.416 .\" 4. Neither the name of the author nor the names of any co-contributors
42 .Bd -ragged -offset indent
50 .Bd -literal -offset indent
61 copper cable, except for the SysKonnect SK-9D41 which supports only
64 It has two R4000 CPU cores and is PCI v2.2 and PCI-X v1.0 compliant.
67 multiple RX and TX DMA rings for QoS applications, rules-based
69 a 256-bit multicast hash filter.
71 provided via value-add firmware updates.
72 The BCM570x supports TBI (ten bit interface) and GMII
78 Most BCM5700-based cards also use the Broadcom BCM5401 or BCM5411 10/100/1000
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H A Dti.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
50 .Bd -literal -offset indent
63 Either chip can be used in either a 32-bit or 64-bit PCI
118 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
130 .Ar full-duplex
132 .Ar half-duplex
139 .Ar full-duplex
141 .Ar half-duplex
146 .Ar full-duplex
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/freebsd-src/contrib/llvm-project/compiler-rt/lib/builtins/
H A Dfp_div_impl.inc1 //===-- fp_div_impl.inc - Floating point division -----------------*- C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements soft-float division with the IEEE-754 default
12 //===----------------------------------------------------------------------===//
16 // The __divXf3__ function implements Newton-Raphson floating point division.
19 // every iteration, the two modes are supported: N full-width iterations (as
20 // it is done for float32 by default) and (N-1) half-width iteration plus one
21 // final full-width iteration. It is expected that half-width integer
26 // Half the bit-size of rep_t
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td1 //===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//
5 // SPDX-Licens
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/freebsd-src/sys/contrib/ncsw/Peripherals/FM/MACSEC/
H A Dfm_macsec_master.h2 * Copyright 2008-2015 Freescale Semiconductor Inc.
168 volatile uint32_t rxsci1h; /**< RX Secure Channel Identifier first half */
169 volatile uint32_t rxsci2h; /**< RX Secure Channel Identifier second half */
171 volatile uint32_t ifio1hs; /**< ifInOctets first half Statistic */
172 volatile uint32_t ifio2hs; /**< ifInOctets second half Statistic */
180 volatile uint32_t inov1hs; /**< InOctetsValidated first half Statistic */
181 volatile uint32_t inov2hs; /**< InOctetsValidated second half Statistic */
182 volatile uint32_t inod1hs; /**< InOctetsDecrypted first half Statistic */
183 volatile uint32_t inod2hs; /**< InOctetsDecrypted second half Statistic */
188 volatile uint32_t rxaninuss[MAX_NUM_OF_SA_PER_SC]; /**< RX AN 0-3 InNotUsingSA Statistic */
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/freebsd-src/contrib/llvm-project/clang/lib/Headers/hlsl/
H A Dhlsl_basic_types.h1 //===----- hlsl_basic_types.h - HLSL definitions for basic types ----
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/freebsd-src/sys/contrib/device-tree/Bindings/dma/
H A Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
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/freebsd-src/contrib/libcbor/src/cbor/
H A Dencoding.h2 * Copyright (c) 2014-2020 Pavel Kalvoda <me@pavelkalvoda.com>
20 * - a logical `value` to encode (except for trivial items such as NULLs)
21 * - an output `buffer` pointer
22 * - a `buffer_size` specification
101 /** Encodes a half-precision float
103 * Since there is no native representation or semantics for half floats
104 * in the language, we use single-precision floats, as every value that
105 * can be expressed as a half-float can also be expressed as a float.
109 * - Infinity, NaN are preserved
110 * - Zero is preserved
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/freebsd-src/sys/dev/qat/include/common/
H A Dadf_pfvf_msg.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
7 * PF<->VF Gen2 Messaging format
9 * The PF has an array of 32-bit PF2VF registers, one for each VF. The
14 * The bottom half is for PF->VF messages. In particular when the first
15 * bit of this register (bit 0) gets set an interrupt will be triggered
17 * The top half is for VF->PF messages. In particular when the first bit
18 * of this half of register (bit 16) gets set an interrupt will be triggered
28 * +-----------------------------------------------+
34 * Message-specific Data/Reserved
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/freebsd-src/contrib/llvm-project/clang/lib/Headers/ppc_wrappers/
H A Dmmintrin.h1 /*===---- mmintrin.h - Implementation of MMX intrinsics on PowerPC ---------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
17 Since PowerPC target doesn't support native 64-bit vector type, we
18 typedef __m64 to 64-bit unsigned long long in MMX intrinsics, which
22 128-bit PowerPC vector first. Power8 introduced direct register
28 efficient standard C or GNU C extensions with 64-bit scalar
29 operations, or 128-bit SSE/Altivec operations, which are more
32 "Please read comment above. Use -DNO_WARN_X86_INTRINSICS to disable this error."
70 /* Convert I to a __m64 object. The integer is zero-extended to 64-bits. */
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Schedule.td1 //===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // InstrSchedModel annotations for out-of-order CPUs.
55 // Register-Memory operation.
57 // Register-Register operation.
131 def WriteCopy : WriteSequence<[WriteLoad, WriteStore]>; // mem->mem copy
141 defm WriteIMul8 : X86SchedWritePair; // Integer 8-bit multiplication.
142 defm WriteIMul16 : X86SchedWritePair; // Integer 16-bit multiplication.
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/freebsd-src/contrib/llvm-project/clang/lib/Sema/
H A DOpenCLBuiltins.td1 //==--- OpenCLBuiltins.td - OpenCL builtin declarations ------
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/freebsd-src/contrib/bc/src/
H A Drand.c9 * https://github.com/imneme/pcg-c
11 * ---------
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