Lines Matching +full:half +full:- +full:bit
1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
7 * PF<->VF Gen2 Messaging format
9 * The PF has an array of 32-bit PF2VF registers, one for each VF. The
14 * The bottom half is for PF->VF messages. In particular when the first
15 * bit of this register (bit 0) gets set an interrupt will be triggered
17 * The top half is for VF->PF messages. In particular when the first bit
18 * of this half of register (bit 16) gets set an interrupt will be triggered
28 * +-----------------------------------------------+
34 * Message-specific Data/Reserved
39 * +-----------------------------------------------+
45 * Message-specific Data/Reserved
48 * A legacy out-of-tree QAT driver allowed for a set of messages not supported
57 * PF<->VF Gen4 Messaging format
59 * Similarly to the gen2 messaging format, 32-bit long registers are used for
61 * 32-bits register to avoid collisions: one for PV to VF messages and one
64 * Both the Interrupt bit and the Message Origin bit retain the same position
65 * and meaning, although non-system messages are now deprecated and not
71 * +-----------------------------------------------+
77 * Message-specific Data/Reserved
80 * interrupt bit on the register where the message was sent.
84 #define ADF_PFVF_INT BIT(0)
85 #define ADF_PFVF_MSGORIGIN_SYSTEM BIT(1)
95 /* PF->VF messages */
105 /* VF->PF messages */
123 /* In-use pattern cleared by receiver */
125 /* Ring to service mapping support for non-standard mappings */
131 /* PF->VF Version Response */
151 /* PF->VF Block Responses */
161 /* PF->VF Block Error Code */
169 /* VF->PF Block Requests */
176 #define ADF_VF2PF_BLOCK_CRC_REQ_MASK BIT(9)
178 /* PF->VF Block Request Types
179 * 0..15 - 32 byte message
180 * 16..23 - 64 byte message
181 * 24..27 - 128 byte message
215 (sizeof(blkmsg) - ADF_PFVF_BLKMSG_HEADER_SIZE)
217 (ADF_PFVF_BLKMSG_HEADER_SIZE + (blkmsg)->hdr.payload_size)
220 /* PF->VF Block message header bytes */