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Searched +full:gcc +full:- +full:ipq4019 (Results 1 – 24 of 24) sorted by relevance

/freebsd-src/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-ipq4019.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-binding
187 gcc: clock-controller@1800000 { global() label
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/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,gcc-ipq4019.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc
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/freebsd-src/sys/contrib/device-tree/Bindings/net/wireless/
H A Dqcom,ath10k.txt4 - compatible: Should be one of the following:
6 * "qcom,ipq4019-wifi"
7 * "qcom,wcn3990-wifi"
10 data along with board specific data via "qcom,ath10k-calibration-data".
13 AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"
15 "qcom,ath10k-calibration-data"). It uses "qcom,ath10k-pre-calibration-data"
18 In general, entry "qcom,ath10k-pre-calibration-data" and
19 "qcom,ath10k-calibration-data" conflict with each other and only one
22 SNOC based devices (i.e. wcn3990) uses compatible string "qcom,wcn3990-wifi".
24 - reg: Address and length of the register set for the device.
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H A Dqcom,ath10k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd-src/sys/contrib/device-tree/Bindings/phy/
H A Dqcom-usb-ipq4019-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robert.marko@sartura.hr>
15 - qcom,usb-ss-ipq4019-phy
16 - qcom,usb-hs-ipq4019-phy
24 reset-names:
26 - const: por_rst
27 - const: srif_rst
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/freebsd-src/sys/contrib/device-tree/Bindings/mtd/
H A Dqcom,nandc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dqcom_nandc.txt4 - compatible: must be one of the following:
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
8 IPQ4019 SoC and it uses BAM DMA
9 * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in
11 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
13 * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in
16 - reg: MMIO address range
17 - clocks: must contain core clock and always on clock
18 - clock-names: must contain "core" for the core clock and "aon" for the
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/freebsd-src/sys/contrib/device-tree/Bindings/crypto/
H A Dqcom-qce.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/qcom-qc
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/freebsd-src/sys/contrib/device-tree/Bindings/usb/
H A Dqcom,dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wesle
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/freebsd-src/sys/contrib/device-tree/Bindings/pci/
H A Dqcom,pcie.txt3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sc8180x" for sc8180x
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H A Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd-src/sys/contrib/device-tree/Bindings/arm/
H A Dqcom-soc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/qcom-soc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
15 qcom,SoC-IP
18 qcom,sdm845-llcc-bwmon
26 pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
28 - compatible
34 - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
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/freebsd-src/sys/dev/qcom_gcc/
H A Dqcom_gcc_ipq4018.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
52 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
89 if (ofw_bus_is_compatible(dev, "qcom,gcc-ipq4019") == 0) in qcom_gcc_ipq4018_probe()
103 sc->dev = dev; in qcom_gcc_ipq4018_attach()
105 sc->reg_rid = 0; in qcom_gcc_ipq4018_attach()
106 sc->reg = bus_alloc_resource_anywhere(dev, SYS_RES_MEMORY, in qcom_gcc_ipq4018_attach()
107 &sc->reg_rid, 0x60000, RF_ACTIVE); in qcom_gcc_ipq4018_attach()
108 if (sc->reg == NULL) { in qcom_gcc_ipq4018_attach()
115 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); in qcom_gcc_ipq4018_attach()
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H A Dqcom_gcc_ipq4018_reset.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
51 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
143 mtx_lock(&sc->mtx); in qcom_gcc_ipq4018_hwreset_assert()
144 reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg); in qcom_gcc_ipq4018_hwreset_assert()
149 bus_write_4(sc->reg, gcc_ipq4019_reset_list[id].reg, reg); in qcom_gcc_ipq4018_hwreset_assert()
150 mtx_unlock(&sc->mtx); in qcom_gcc_ipq4018_hwreset_assert()
166 mtx_lock(&sc->mtx); in qcom_gcc_ipq4018_hwreset_is_asserted()
167 reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg); in qcom_gcc_ipq4018_hwreset_is_asserted()
172 mtx_unlock(&sc->mtx); in qcom_gcc_ipq4018_hwreset_is_asserted()
H A Dqcom_gcc_ipq4018_clock.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
52 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
130 /* read-only div table */
185 * P_FEPLL125 - 125MHz
186 * P_FEPLL125DLY - 125MHz
187 * P_FEPLL200 - 200MHz
188 * "fepll500" - 500MHz
192 * P_DDRPLL - 192MHz
203 * FEPLL - 48MHz (xo) input, 4GHz output
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/freebsd-src/sys/contrib/device-tree/Bindings/firmware/
H A Dqcom,scm.txt9 - compatible: must contain one of the following:
10 * "qcom,scm-apq8064"
11 * "qcom,scm-apq8084"
12 * "qcom,scm-ipq4019"
13 * "qcom,scm-ipq806x"
14 * "qcom,scm-ipq8074"
15 * "qcom,scm-mdm9607"
16 * "qcom,scm-msm8226"
17 * "qcom,scm-msm8660"
18 * "qcom,scm-msm8916"
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H A Dqcom,scm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd-src/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schema
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/freebsd-src/sys/dts/arm/
H A Dqcom-ipq4019-ethernet.dtsi1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
28 #include <dt-bindings/net/qcom-qca807x.h>
33 #address-cells = <1>;
34 #size-cells = <0>;
35 compatible = "qcom,ipq4019-mdio";
40 ess-switch@c000000 {
41 compatible = "qcom,ess-switch";
43 resets = <&gcc ESS_RESET>;
44 reset-names = "ess_rst";
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/freebsd-src/sys/contrib/device-tree/src/arm64/qcom/
H A Dipq6018.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc
384 gcc: gcc@1800000 { global() label
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H A Dipq9574.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gc
295 gcc: clock-controller@1800000 { global() label
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H A Dipq8074.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq807
357 gcc: gcc@1800000 { global() label
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H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispc
805 gcc: clock-controller@1400000 { global() label
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/freebsd-src/sys/contrib/dev/athk/ath10k/
H A Dahb.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved.
17 { .compatible = "qcom,ipq4019-wifi",
30 return &ath10k_pci_priv(ar)->ahb[0]; in ath10k_ahb_priv()
37 iowrite32(value, ar_ahb->mem + offset); in ath10k_ahb_write32()
44 return ioread32(ar_ahb->mem + offset); in ath10k_ahb_read32()
51 return ioread32(ar_ahb->gcc_mem + offset); in ath10k_ahb_gcc_read32()
58 iowrite32(value, ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_write32()
65 return ioread32(ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_read32()
75 if (ar->hw_rev == ATH10K_HW_QCA4019) in ath10k_ahb_get_num_banks()
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