Lines Matching +full:gcc +full:- +full:ipq4019
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
52 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
130 /* read-only div table */
185 * P_FEPLL125 - 125MHz
186 * P_FEPLL125DLY - 125MHz
187 * P_FEPLL200 - 200MHz
188 * "fepll500" - 500MHz
192 * P_DDRPLL - 192MHz
203 * FEPLL - 48MHz (xo) input, 4GHz output
204 * DDRPLL - 48MHz (xo) input, 5.376GHz output
215 * Note - the APSS DIV code only needs the frequency and pre-divisor,
399 * Read-only divisor table clocks.
413 0x1b000, 5, 0, -1, -1, 0, 0, &audio_clk_src_freq_tbl[0]),
415 gcc_xo_200_parents, 0x200c, 5, 0, -1, -1, 0, 0,
418 gcc_xo_200_parents, 0x3000, 5, 0, -1, -1, 0, 0,
421 gcc_xo_200_spi_parents, 0x2024, 5, 8, -1, -1, 0, 0,
424 gcc_xo_200_spi_parents, 0x3014, 5, 8, -1, -1, 0, 0,
427 gcc_xo_200_spi_parents, 0x2044, 5, 16, -1, -1, 0, 0,
430 gcc_xo_200_spi_parents, 0x3034, 5, 16, -1, -1, 0, 0,
433 5, 8, -1, -1, 0, 0,
436 5, 8, -1, -1, 0, 0,
439 5, 8, -1, -1, 0, 0,
442 gcc_xo_sdcc1_500_parents, 0x18004, 5, 0, -1, -1, 0, 0,
445 0x1900c, 5, 0, -1, 2, 0,
449 gcc_xo_200_500_parents, 0x19014, 5, 0, -1, -1, 0,
452 gcc_xo_200_parents, 0x1e000, 5, 0, -1, -1, 0, 0,
455 gcc_xo_125_dly_parents, 0x12000, 5, 0, -1, -1, 0, 0,
458 0x1f000, 5, 0, -1, -1, 0, 0,
461 0x20000, 5, 0, -1, -1, 0, 0,
464 gcc_xo_200_500_parents, 0x21024, 5, 0, -1, -1, 0, 0,
598 /* Note - yes, these two have the same registers in linux */
609 /* Note - yes, these two have the same registers in linux */
632 rv = qcom_clk_fepll_register(sc->clkdom, fepll_tbl + i); in qcom_gcc_ipq4018_clock_init_fepll()
644 rv = qcom_clk_fdiv_register(sc->clkdom, fdiv_tbl + i); in qcom_gcc_ipq4018_clock_init_fdiv()
656 rv = qcom_clk_apssdiv_register(sc->clkdom, apssdiv_tbl + i); in qcom_gcc_ipq4018_clock_init_apssdiv()
668 rv = qcom_clk_rcg2_register(sc->clkdom, rcg2_tbl + i); in qcom_gcc_ipq4018_clock_init_rcg2()
680 rv = qcom_clk_branch2_register(sc->clkdom, branch2_tbl + i); in qcom_gcc_ipq4018_clock_init_branch2()
692 rv = qcom_clk_ro_div_register(sc->clkdom, ro_div_tbl + i); in qcom_gcc_ipq4018_clock_init_ro_div()
704 *val = bus_read_4(sc->reg, addr); in qcom_gcc_ipq4018_clock_read()
714 bus_write_4(sc->reg, addr, val); in qcom_gcc_ipq4018_clock_write()
726 reg = bus_read_4(sc->reg, addr); in qcom_gcc_ipq4018_clock_modify()
729 bus_write_4(sc->reg, addr, reg); in qcom_gcc_ipq4018_clock_modify()
737 sc->clkdom = clkdom_create(sc->dev); in qcom_gcc_ipq4018_clock_setup()
748 clkdom_finit(sc->clkdom); in qcom_gcc_ipq4018_clock_setup()
757 mtx_lock(&sc->mtx); in qcom_gcc_ipq4018_clock_lock()
766 mtx_unlock(&sc->mtx); in qcom_gcc_ipq4018_clock_unlock()