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/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dfixed-mmio-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple memory mapped IO fixed-rate clock sources
10 This binding describes a fixed-rate clock for which the frequency can
11 be read from a single 32-bit memory mapped I/O register.
17 - Jan Kotas <jank@cadence.com>
21 const: fixed-mmio-clock
26 "#clock-cells":
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H A Dfixed-mmio-clock.txt1 Binding for simple memory mapped io fixed-rate clock sources.
2 The driver reads a clock frequency value from a single 32-bit memory mapped
3 I/O register and registers it as a fixed rate clock.
7 This binding uses the common clock binding[1].
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible : shall be "fixed-mmio-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - reg : Address and length of the clock value register set.
17 - clock-output-names : From common clock binding.
21 #clock-cells = <0>;
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/freebsd-src/sys/contrib/device-tree/src/arc/
H A Dhaps_hs.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
5 /dts-v1/;
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&core_intc>;
24 … "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
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/freebsd-src/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 #include "armada-370-xp.dtsi"
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
38 internal-regs {
40 compatible = "marvell,armada-xp-sdram-controller";
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H A Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controlle
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H A Darmada-375.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controlle
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/freebsd-src/sys/contrib/device-tree/Bindings/arm/calxeda/
H A Dhb-sregs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Calxeda Highbank system has a block of MMIO registers controlling
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-sregs
28 - compatible
29 - reg
34 - |
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/freebsd-src/sys/contrib/device-tree/src/arm/sigmastar/
H A Dmstar-v7.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
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/freebsd-src/sys/contrib/device-tree/src/arm/nspire/
H A Dnspire.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&intc>;
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,arm926ej-
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/freebsd-src/sys/contrib/device-tree/Bindings/mtd/
H A Dqcom_nandc.txt4 - compatible: must be one of the following:
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in
11 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
13 * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in
16 - reg: MMIO address range
17 - clocks: must contain core clock and always on clock
18 - clock-names: must contain "core" for the core clock and "aon" for the
19 always on clock
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/arm/
H A Drtsm_ve-motherboard.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 v2m_clk24mhz: clock-24000000 {
12 compatible = "fixed-clock";
13 #clock-cell
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H A Dfoundation-v8.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Foundation-v8A";
16 compatible = "arm,foundation-aarch64", "arm,vexpress";
17 interrupt-paren
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/freebsd-src/sys/contrib/device-tree/Bindings/display/imx/
H A Dfsl-imx-drm.txt8 - compatible: Should be "fsl,imx-display-subsystem"
9 - ports: Should contain a list of phandles pointing to display interface ports
14 display-subsystem {
15 compatible = "fsl,imx-display-subsystem";
24 - compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
25 - imx51
26 - imx53
27 - imx6q
28 - imx6qp
29 - reg: should be register base and length as documented in the
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/freebsd-src/sys/contrib/device-tree/src/arm/microchip/
H A Dsama7g5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controlle
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/freebsd-src/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
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H A Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&intc>;
16 osc24M: clk-24M {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <24000000>;
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/freebsd-src/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-binding
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/freebsd-src/sys/contrib/device-tree/Bindings/pci/
H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generi
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H A Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx1.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include "imx1-pinfunc.h"
7 #include <dt-bindings/clock/imx1-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-binding
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/freebsd-src/sys/contrib/device-tree/src/arm64/microchip/
H A Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-paren
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm/renesas/
H A Dr8a77470.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a7747
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H A Dr8a7745.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Cogent Embedded Inc.
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-binding
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/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8ulp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8ulp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controlle
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm/nxp/lpc/
H A Dlpc32xx.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
9 #include <dt-bindings/clock/lpc32xx-clock.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 interrupt-parent = <&mic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "arm,arm926ej-s";
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