Lines Matching +full:fixed +full:- +full:mmio +full:- +full:clock
5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
15 - ranges: ranges describing the MMIO registers to control the PCIe
18 - msi-parent: Link to the hardware entity that serves as the Message
21 The ranges describing the MMIO registers have the following layout:
27 * r is a 32-bits value that gives the offset of the MMIO
31 * s is a 32-bits value that give the size of this MMIO
52 Since the location and size of the different MBus windows is not fixed in
57 In addition, the device tree node must have sub-nodes describing each
60 - reg: used only for interrupt mapping, so only the first four bytes
62 - assigned-addresses: reference to the MMIO registers used to control
64 - clocks: the clock associated to this PCIe interface
65 - marvell,pcie-port: the physical PCIe port number
66 - status: either "disabled" or "okay"
67 - device_type, set to "pci"
68 - #address-cells, set to <3>
69 - #size-cells, set to <2>
70 - #interrupt-cells, set to <1>
71 - ranges, translating the MBus windows ranges of the parent node into
73 - interrupt-map-mask and interrupt-map, standard PCI properties to
77 - marvell,pcie-lane: the physical PCIe lane number, for ports having
80 - num-lanes: number of SerDes PCIe lanes for this link (1 or 4)
81 - reset-gpios: optional GPIO to PERST#
82 - reset-delay-us: delay in us to wait after reset de-assertion, if not
84 - interrupt-names: list of interrupt names, supported are:
85 - "intx" - interrupt line triggered by one of the legacy interrupt
86 - interrupts or interrupts-extended: List of the interrupt sources which
87 corresponding to the "interrupt-names". If non-empty then also additional
88 'interrupt-controller' subnode must be defined.
92 pcie-controller {
93 compatible = "marvell,armada-xp-pcie";
96 #address-cells = <3>;
97 #size-cells = <2>;
99 bus-range = <0x00 0xff>;
100 msi-parent = <&mpic>;
139 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
141 #address-cells = <3>;
142 #size-cells = <2>;
143 #interrupt-cells = <1>;
146 interrupt-map-mask = <0 0 0 0>;
147 interrupt-map = <0 0 0 0 &mpic 58>;
148 marvell,pcie-port = <0>;
149 marvell,pcie-lane = <0>;
150 num-lanes = <1>;
151 /* low-active PERST# reset on GPIO 25 */
152 reset-gpios = <&gpio0 25 1>;
154 reset-delay-us = <20000>;
160 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
162 #address-cells = <3>;
163 #size-cells = <2>;
164 #interrupt-cells = <1>;
167 interrupt-map-mask = <0 0 0 0>;
168 interrupt-map = <0 0 0 0 &mpic 59>;
169 marvell,pcie-port = <0>;
170 marvell,pcie-lane = <1>;
171 num-lanes = <1>;
177 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
179 #address-cells = <3>;
180 #size-cells = <2>;
181 #interrupt-cells = <1>;
184 interrupt-map-mask = <0 0 0 0>;
185 interrupt-map = <0 0 0 0 &mpic 60>;
186 marvell,pcie-port = <0>;
187 marvell,pcie-lane = <2>;
188 num-lanes = <1>;
194 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
196 #address-cells = <3>;
197 #size-cells = <2>;
198 #interrupt-cells = <1>;
201 interrupt-map-mask = <0 0 0 0>;
202 interrupt-map = <0 0 0 0 &mpic 61>;
203 marvell,pcie-port = <0>;
204 marvell,pcie-lane = <3>;
205 num-lanes = <1>;
211 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
213 #address-cells = <3>;
214 #size-cells = <2>;
215 #interrupt-cells = <1>;
218 interrupt-map-mask = <0 0 0 0>;
219 interrupt-map = <0 0 0 0 &mpic 62>;
220 marvell,pcie-port = <1>;
221 marvell,pcie-lane = <0>;
222 num-lanes = <1>;
228 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
230 #address-cells = <3>;
231 #size-cells = <2>;
232 #interrupt-cells = <1>;
235 interrupt-map-mask = <0 0 0 0>;
236 interrupt-map = <0 0 0 0 &mpic 63>;
237 marvell,pcie-port = <1>;
238 marvell,pcie-lane = <1>;
239 num-lanes = <1>;
245 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
247 #address-cells = <3>;
248 #size-cells = <2>;
249 #interrupt-cells = <1>;
252 interrupt-map-mask = <0 0 0 0>;
253 interrupt-map = <0 0 0 0 &mpic 64>;
254 marvell,pcie-port = <1>;
255 marvell,pcie-lane = <2>;
256 num-lanes = <1>;
262 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
264 #address-cells = <3>;
265 #size-cells = <2>;
266 #interrupt-cells = <1>;
269 interrupt-map-mask = <0 0 0 0>;
270 interrupt-map = <0 0 0 0 &mpic 65>;
271 marvell,pcie-port = <1>;
272 marvell,pcie-lane = <3>;
273 num-lanes = <1>;
279 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
281 #address-cells = <3>;
282 #size-cells = <2>;
283 #interrupt-cells = <1>;
286 interrupt-map-mask = <0 0 0 0>;
287 interrupt-map = <0 0 0 0 &mpic 99>;
288 marvell,pcie-port = <2>;
289 marvell,pcie-lane = <0>;
290 num-lanes = <1>;
296 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
298 #address-cells = <3>;
299 #size-cells = <2>;
300 #interrupt-cells = <1>;
303 interrupt-map-mask = <0 0 0 0>;
304 interrupt-map = <0 0 0 0 &mpic 103>;
305 marvell,pcie-port = <3>;
306 marvell,pcie-lane = <0>;
307 num-lanes = <1>;