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/freebsd-src/sys/contrib/device-tree/Bindings/serial/
H A Dfsl-imx-uart.txt4 - compatible : Should be "fsl,<soc>-uart"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain uart interrupt
9 - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
10 in DCE mode by default.
11 - fsl,inverted-tx , fsl,inverted-rx : Indicate that the hardware attached
15 - rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
16 linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485
17 you must enable either the "uart-has-rtscts" or the "rts-gpios"
18 properties. In case you use "uart-has-rtscts" the signal that controls
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H A Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <festevam@gmail.com>
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
17 - items:
18 - enum:
19 - fsl,imx25-uart
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/freebsd-src/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2014-2022 Toradex
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pwm/pwm.h>
19 /delete-property/ mmc3;
29 compatible = "pwm-backligh
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H A Dimx6dl-eckelmann-ci4x10.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
15 compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl";
18 stdout-path = &uart3;
26 rmii_clk: clock-rmii {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <50000000>;
31 clock-output-names = "enet_ref_pad";
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H A Dimx6ull-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2018-2022 Toradex
16 compatible = "pwm-backlight";
17 brightness-levels = <0 4 8 16 32 64 128 255>;
18 default-brightness-level = <6>;
19 enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_gpio_bl_on>;
22 power-supply = <&reg_3v3>;
28 compatible = "gpio-usb-b-connector", "usb-b-connector";
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H A Dimx6qdl-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright 2014-2022 Toradex
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pwm/pwm.h>
18 /delete-property/ mmc2;
19 /delete-property/ mmc3;
23 compatible = "pwm-backlight";
24 brightness-level
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H A Dmba6ulx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 model = "TQ-Systems MBA6ULx Baseboard";
18 stdout-pat
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H A Dimx6q-arm2.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
13 compatible = "fsl,imx6q-arm2", "fsl,imx6q";
20 reg_3p3v: regulator-3p3v {
21 compatible = "regulator-fixed";
22 regulator-name = "3P3V";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
25 regulator-always-on;
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H A Dimx53-cx9020.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * based on imx53-qsb.dts
7 /dts-v1/;
15 stdout-path = &uart2;
24 display-0 {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 compatible = "fsl,imx-parallel-display";
28 interface-pix-fmt = "rgb24";
29 pinctrl-names = "default";
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H A Dimx7-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2016-2022 Toradex
6 #include <dt-bindings/pwm/pwm.h>
15 brightness-levels = <0 45 63 88 119 158 203 255>;
16 compatible = "pwm-backlight";
17 default-brightnes
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H A Dimx7d-meerkat96.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 /dts-v1/;
12 compatible = "novtech,imx7d-meerkat96", "fsl,imx7d";
15 stdout-path = &uart6;
23 reg_wlreg_on: regulator-wlreg-on {
24 compatible = "regulator-fixed";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_wlreg_on>;
27 regulator-name = "wlreg_on";
28 regulator-min-microvolt = <3300000>;
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H A Dimx7s-warp.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
14 compatible = "element14,imx7s-warp", "fsl,imx7s";
21 gpio-keys {
22 compatible = "gpio-keys";
23 pinctrl-0 = <&pinctrl_gpio>;
30 wakeup-sourc
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/freebsd-src/share/misc/
H A Dscsi_modes1 # SCSI mode page data base.
35 # 'i' is a byte-sized integral types, followed by a field width of
38 # 'b' is a bit-sized integral type
39 # 't' is a bitfield type- followed by a bit field width
42 # 'z' values are null-padded strings
78 {Autoload Mode} t3
81 {Extended Self-Test Completion Time} i2
95 0x02 "Disconnect-Reconnect" {
111 0x16 "Extended Device-Type Specific";
154 0x18 "Protocol-Specific Logical Unit";
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/freebsd-src/sys/contrib/device-tree/Bindings/pinctrl/
H A Dnvidia,tegra20-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra20-pinmux
19 - description: tri-state registers
20 - description: mux register
21 - description: pull-up/down registers
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H A Dnvidia,tegra20-pinmux.txt4 - compatible: "nvidia,tegra20-pinmux"
5 - reg: Should contain the register physical address and length for each of
6 the tri-state, mux, pull-up/down, and pad control register sets.
8 Please refer to pinctrl-bindings.txt in this directory for details of the
16 parameters, such as pull-up, tristate, drive strength, etc.
30 Required subnode-properties:
31 - nvidia,pins : An array of strings. Each string contains the name of a pin or
34 Optional subnode-properties:
35 - nvidia,function: A string containing the name of the function to mux to the
38 - nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
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/freebsd-src/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra20-trimslice.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
7 #include "tegra20-cpu-opp.dtsi"
20 stdout-path = "serial0:115200n8";
31 vdd-suppl
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H A Dtegra20-tamonten.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 stdout-path = "serial0:115200n8";
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
34 pinctrl-names = "default";
35 pinctrl-0 = <&state_default>;
92 nvidia,pins = "dtb", "dtc", "dte";
206 "dtc", "dte", "gpu", "sdio1",
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H A Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
7 #include "tegra20-cpu-opp.dtsi"
8 #include "tegra20-cpu-opp-microvolt.dtsi"
21 stdout-path = "serial0:115200n8";
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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H A Dtegra20-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0
22 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
23 nvidia,hpd-gpio =
25 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
26 vdd-supply = <&reg_3v3_avdd_hdmi>;
31 lan-reset-
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H A Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-op
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H A Dtegra20-seaboard.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-supply = <&hdmi_pll_reg>;
39 hdmi-supply = <&vdd_hdmi>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
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/freebsd-src/sys/dev/mii/
H A Drgephyreg.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
55 #define RGEPHY_BMCR_FDX 0x0100 /* Duplex mode */
121 #define RGEPHY_1000CTL_RD 0x0400 /* Repeater/DTE */
140 #define RGEPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
141 #define RGEPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
142 #define RGEPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
143 #define RGEPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
172 #define RGEPHY_F_PCR1_MDI_MM 0x0200 /* MDI / MDIX Manual Mode */
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H A Dmii.h3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
50 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
58 #define BMCR_FDX 0x0100 /* Set duplex mode */
68 #define MII_BMSR 0x01 /* Basic mode status register (ro) */
128 #define ANAR_X_FD 0x0020 /* local device supports 1000BASE-X FD */
129 #define ANAR_X_HD 0x0040 /* local device supports 1000BASE-X HD */
153 #define ANLPAR_X_FD 0x0020 /* local device supports 1000BASE-X FD */
154 #define ANLPAR_X_HD 0x0040 /* local device supports 1000BASE-X HD */
164 #define ANER_LPNP 0x0008 /* link parter next page-able */
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/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-phyboard-polis-rdk.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pci
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/freebsd-src/sys/dev/isci/scil/
H A Dsati_mode_pages.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
58 * @brief This file contains the mode page constants and data for the mode
85 SCSI_MODE_PAGE_READ_WRITE_ERROR, // Byte 0 - Page Code, SPF(0), PS(0)
86 SCSI_MODE_PAGE_01_LENGTH-2, // Byte 1 - Page Length
87 0x80, // Byte 2 - AWRE, ARRE, TB, RC, EER, PER, DTE, DCR
88 0x00, // Byte 3 - Read Retry Count
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