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Searched full:devcfg (Results 1 – 13 of 13) sorted by relevance

/freebsd-src/share/man/man4/man4.arm/
H A Ddevcfg.429 .Nm devcfg
32 .Cd device devcfg
35 .Pa /dev/devcfg
44 When the PL asserts the DONE signal, the devcfg driver will enable the level
50 cat design.bit.bin > /dev/devcfg
85 .It Pa /dev/devcfg
H A DMakefile9 devcfg.4 \
/freebsd-src/sys/contrib/device-tree/Bindings/fpga/
H A Dxilinx-zynq-fpga-mgr.txt4 - compatible: should contain "xlnx,zynq-devcfg-1.0"
12 devcfg: devcfg@f8007000 {
13 compatible = "xlnx,zynq-devcfg-1.0";
H A Dxilinx-zynq-fpga-mgr.yaml14 const: xlnx,zynq-devcfg-1.0
45 devcfg: devcfg@f8007000 {
46 compatible = "xlnx,zynq-devcfg-1.0";
H A Dfpga-region.txt351 compatible = "xlnx,zynq-devcfg-1.0";
/freebsd-src/sys/arm/xilinx/
H A Dzy7_devcfg.c30 * Zynq-7000 Devcfg driver. This allows programming the PL (FPGA) section
133 .d_name = "devcfg",
136 /* Devcfg block registers. */
401 /* Set devcfg control register. */ in zy7_devcfg_init_hw()
587 /* Program devcfg's DMA engine. The ordering of these in zy7_devcfg_write()
702 device_set_desc(dev, "Zynq devcfg block"); in zy7_devcfg_probe()
752 /* Create /dev/devcfg */ in zy7_devcfg_attach()
754 UID_ROOT, GID_WHEEL, 0600, "devcfg"); in zy7_devcfg_attach()
756 device_printf(dev, "failed to create /dev/devcfg"); in zy7_devcfg_attach()
764 /* Unlock devcfg register in zy7_devcfg_attach()
[all...]
H A Dzy7_slcr.c177 * is controlled by a sysctl in the devcfg driver.
/freebsd-src/sys/dev/bwn/
H A Dif_bwn_pci.c178 if (bwn_pci_find_devcfg(dev, &sc->devcfg, &ident)) in bwn_pci_attach()
208 return (sc->devcfg->bridge_hwcfg); in bwn_pci_probe_nomatch()
215 return (sc->devcfg->bridge_hwtable);
222 return (sc->devcfg->bridge_hwprio);
H A Dif_bwn_pcivar.h39 const struct bwn_pci_devcfg *devcfg; /**< bwn device config */ member
/freebsd-src/sys/dev/oce/
H A Doce_hw.c508 reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL); in oce_hw_intr_enable()
510 OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg); in oce_hw_intr_enable()
523 reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL); in oce_hw_intr_disable()
525 OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg); in oce_hw_intr_disable()
H A Doce_if.c2399 ue_low = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_LOW); in oce_detect_hw_error()
2400 ue_high = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_HIGH); in oce_detect_hw_error()
2401 ue_low_mask = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_LOW_MASK); in oce_detect_hw_error()
2402 ue_high_mask = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_HI_MASK); in oce_detect_hw_error()
/freebsd-src/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-7000.dtsi39 fpga-mgr = <&devcfg>;
366 devcfg: devcfg@f8007000 { label
367 compatible = "xlnx,zynq-devcfg-1.0";
/freebsd-src/sys/dts/arm/
H A Dzynq-7000.dtsi72 devcfg: devcfg@7000 { label