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/llvm-project/lld/test/ELF/
H A Darm-plt-reloc.s72 // DSO-NEXT: 10240: d4 d4 d4 d4 .word 0xd4d4d4d4
73 // DSO-NEXT: 10244: d4 d4 d4 d4 .word 0xd4d4d4d4
74 // DSO-NEXT: 10248: d4 d4 d4 d4 .word 0xd4d4d4d4
75 // DSO-NEXT: 1024c: d4 d4 d4 d4 .word 0xd4d4d4d4
80 // DSO-NEXT: 1025c: d4 d4 d4 d4 .word 0xd4d4d4d4
85 // DSO-NEXT: 1026c: d4 d4 d4 d4 .word 0xd4d4d4d4
90 // DSO-NEXT: 1027c: d4 d4 d4 d4 .word 0xd4d4d4d4
151 // CHECKHIGH-NEXT: 2010: d4 d4 d4 d4 .word 0xd4d4d4d4
152 // CHECKHIGH-NEXT: 2014: d4 d4 d4 d4 .word 0xd4d4d4d4
153 // CHECKHIGH-NEXT: 2018: d4 d4 d4 d4 .word 0xd4d4d4d4
[all …]
H A Darm-gnu-ifunc-plt.s52 // DISASM-NEXT: 20210: d4 d4 d4 d4 .word 0xd4d4d4d4
53 // DISASM-NEXT: 20214: d4 d4 d4 d4 .word 0xd4d4d4d4
54 // DISASM-NEXT: 20218: d4 d4 d4 d4 .word 0xd4d4d4d4
55 // DISASM-NEXT: 2021c: d4 d4 d4 d4 .word 0xd4d4d4d4
59 // DISASM-NEXT: 2022c: d4 d4 d4 d4 .word 0xd4d4d4d4
63 // DISASM-NEXT: 2023c: d4 d4 d4 d4 .word 0xd4d4d4d4
68 // DISASM-NEXT: 2024c: d4 d4 d4 d4 .word 0xd4d4d4d4
72 // DISASM-NEXT: 2025c: d4 d4 d4 d4 .word 0xd4d4d4d4
H A Darm-thumb-plt-range-thunk-os.s95 // CHECK4-NEXT: 4000020: d4 d4 d4 d4 .word 0xd4d4d4d4
96 // CHECK4-NEXT: 4000024: d4 d4 d4 d4 .word 0xd4d4d4d4
97 // CHECK4-NEXT: 4000028: d4 d4 d4 d4 .word 0xd4d4d4d4
98 // CHECK4-NEXT: 400002c: d4 d4 d4 d4 .word 0xd4d4d4d4
102 // CHECK4-NEXT: 400003c: d4 d4 d4 d4 .word 0xd4d4d4d4
106 // CHECK4-NEXT: 400004c: d4 d4 d4 d4 .word 0xd4d4d4d4
110 // CHECK4-NEXT: 400005c: d4 d4 d4 d4 .word 0xd4d4d4d4
H A Darm-thunk-multipass-plt.s85 // CHECK-PLT-NEXT: d00030: d4 d4 d4 d4 .word 0xd4d4d4d4
86 // CHECK-PLT-NEXT: d00034: d4 d4 d4 d4 .word 0xd4d4d4d4
87 // CHECK-PLT-NEXT: d00038: d4 d4 d4 d4 .word 0xd4d4d4d4
88 // CHECK-PLT-NEXT: d0003c: d4 d4 d4 d4 .word 0xd4d4d4d4
92 // CHECK-PLT-NEXT: d0004c: d4 d4 d4 d4 .word 0xd4d4d4d4
96 // CHECK-PLT-NEXT: d0005c: d4 d4 d4 d4 .word 0xd4d4d4d4
H A Darm-thumb-plt-reloc.s81 // DSO-NEXT: 10240: d4 d4 d4 d4 .word 0xd4d4d4d4
82 // DSO-NEXT: 10244: d4 d4 d4 d4 .word 0xd4d4d4d4
83 // DSO-NEXT: 10248: d4 d4 d4 d4 .word 0xd4d4d4d4
84 // DSO-NEXT: 1024c: d4 d4 d4 d4 .word 0xd4d4d4d4
89 // DSO-NEXT: 1025c: d4 d4 d4 d4 .word 0xd4d4d4d4
94 // DSO-NEXT: 1026c: d4 d4 d4 d4 .word 0xd4d4d4d4
99 // DSO-NEXT: 1027c: d4 d4 d4 d4 .word 0xd4d4d4d4
H A Darm-thumb-interwork-thunk.s297 // CHECK-ARM-PLT-NEXT: 1620: d4 d4 d4 d4 .word 0xd4d4d4d4
298 // CHECK-ARM-PLT-NEXT: 1624: d4 d4 d4 d4 .word 0xd4d4d4d4
299 // CHECK-ARM-PLT-NEXT: 1628: d4 d4 d4 d4 .word 0xd4d4d4d4
300 // CHECK-ARM-PLT-NEXT: 162c: d4 d4 d4 d4 .word 0xd4d4d4d4
304 // CHECK-ARM-PLT-NEXT: 163c: d4 d4 d4 d4 .word 0xd4d4d4d4
308 // CHECK-ARM-PLT-NEXT: 164c: d4 d4 d4 d4 .word 0xd4d4d4d4
312 // CHECK-ARM-PLT-NEXT: 165c: d4 d4 d4 d4 .word 0xd4d4d4d4
316 // CHECK-ARM-PLT-NEXT: 166c: d4 d4 d4 d4 .word 0xd4d4d4d4
320 // CHECK-ARM-PLT-NEXT: 167c: d4 d4 d4 d4 .word 0xd4d4d4d4
324 // CHECK-ARM-PLT-NEXT: 168c: d4 d4 d4 d4 .word 0xd4d4d4d4
[all …]
H A Darm-thunk-re-add.s108 // CHECK3-NEXT: 1100030: d4 d4 d4 d4 .word 0xd4d4d4d4
109 // CHECK3-NEXT: 1100034: d4 d4 d4 d4 .word 0xd4d4d4d4
110 // CHECK3-NEXT: 1100038: d4 d4 d4 d4 .word 0xd4d4d4d4
111 // CHECK3-NEXT: 110003c: d4 d4 d4 d4 .word 0xd4d4d4d4
115 // CHECK3-NEXT: 110004c: d4 d4 d4 d4 .word 0xd4d4d4d4
119 // CHECK3-NEXT: 110005c: d4 d4 d4 d4 .word 0xd4d4d4d4
H A Darm-thumb-interwork-shared.s44 // CHECK-NEXT: 10220: d4 d4 d4 d4 .word 0xd4d4d4d4
51 // CHECK-NEXT: 1023c: d4 d4 d4 d4 .word 0xd4d4d4d4
55 // CHECK-NEXT: 1024c: d4 d4 d4 d4 .word 0xd4d4d4d4
/llvm-project/llvm/test/MC/ARM/
H A Dneon-bitwise-encoding.s176 vand d4, d7, d3
177 vand.8 d4, d7, d3
178 vand.16 d4, d7, d3
179 vand.32 d4, d7, d3
180 vand.64 d4, d7, d3
182 vand.i8 d4, d7, d3
183 vand.i16 d4, d7, d3
184 vand.i32 d4, d7, d3
185 vand.i64 d4, d7, d3
187 vand.s8 d4, d7, d3
[all …]
H A Dneon-vld-vst-align.s2978 vld3.8 {d0, d2, d4}, [r4]
2979 vld3.8 {d0, d2, d4}, [r4:16]
2980 vld3.8 {d0, d2, d4}, [r4:32]
2981 vld3.8 {d0, d2, d4}, [r4:64]
2982 vld3.8 {d0, d2, d4}, [r4:128]
2983 vld3.8 {d0, d2, d4}, [r4:256]
2985 @ CHECK: vld3.8 {d0, d2, d4}, [r4] @ encoding: [0x24,0xf9,0x0f,0x05]
2987 @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:16]
2990 @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:32]
2992 @ CHECK: vld3.8 {d0, d2, d4}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x05]
[all …]
H A Dneon-mul-encoding.s106 vmul.i16 d0, d4[2]
110 vmul.s32 d4, d3[1]
111 vmul.u32 d5, d4[0]
114 vmul.i16 q0, d4[2]
119 vmul.u32 q5, d4[0]
122 vmul.i16 d9, d0, d4[2]
126 vmul.s32 d5, d4, d3[1]
127 vmul.u32 d4, d5, d4[0]
130 vmul.i16 q9, q0, d4[2]
135 vmul.u32 q4, q5, d4[0]
[all …]
H A Dsingle-precision-fp.s6 vsub.f64 d2, d3, d4
7 vdiv.f64 d4, d5, d6
13 @ CHECK-ERRORS-NEXT: vsub.f64 d2, d3, d4
15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
23 vnmla.f64 d5, d4, d3
26 vfms.f64 d4, d5, d6
34 @ CHECK-ERRORS-NEXT: vnmla.f64 d5, d4, d3
40 @ CHECK-ERRORS-NEXT: vfms.f64 d4, d5, d6
58 vabs.f64 d4, d5
66 @ CHECK-ERRORS-NEXT: vabs.f64 d4, d5
[all …]
H A Dthumb-fp-armv8.s41 vcvtp.s32.f64 s0, d4
42 @ CHECK: vcvtp.s32.f64 s0, d4 @ encoding: [0xbe,0xfe,0xc4,0x0b]
58 vcvtp.u32.f64 s0, d4
59 @ CHECK: vcvtp.u32.f64 s0, d4 @ encoding: [0xbe,0xfe,0x44,0x0b]
77 vseleq.f64 d2, d4, d8
78 @ CHECK: vseleq.f64 d2, d4, d8 @ encoding: [0x04,0xfe,0x08,0x2b]
92 vminnm.f64 d4, d6, d9
93 @ CHECK: vminnm.f64 d4, d6, d9 @ encoding: [0x86,0xfe,0x49,0x4b]
115 vrinta.f64 d3, d4
116 @ CHECK: vrinta.f64 d3, d4 @ encoding: [0xb8,0xfe,0x44,0x3b]
[all …]
H A Dfp-armv8.s38 vcvtp.s32.f64 s0, d4
39 @ CHECK: vcvtp.s32.f64 s0, d4 @ encoding: [0xc4,0x0b,0xbe,0xfe]
55 vcvtp.u32.f64 s0, d4
56 @ CHECK: vcvtp.u32.f64 s0, d4 @ encoding: [0x44,0x0b,0xbe,0xfe]
74 vseleq.f64 d2, d4, d8
75 @ CHECK: vseleq.f64 d2, d4, d8 @ encoding: [0x08,0x2b,0x04,0xfe]
89 vminnm.f64 d4, d6, d9
90 @ CHECK: vminnm.f64 d4, d6, d9 @ encoding: [0x49,0x4b,0x86,0xfe]
109 vrinta.f64 d3, d4
110 @ CHECK: vrinta.f64 d3, d4 @ encoding: [0x44,0x3b,0xb8,0xfe]
[all …]
H A Dfp-armv8-m.s45 vcvtp.s32.f64 s0, d4
46 @ CHECK-V81M: vcvtp.s32.f64 s0, d4 @ encoding: [0xbe,0xfe,0xc4,0x0b]
62 vcvtp.u32.f64 s0, d4
63 @ CHECK-V81M: vcvtp.u32.f64 s0, d4 @ encoding: [0xbe,0xfe,0x44,0x0b]
81 vseleq.f64 d2, d4, d8
82 @ CHECK-V81M: vseleq.f64 d2, d4, d8 @ encoding: [0x04,0xfe,0x08,0x2b]
96 vminnm.f64 d4, d6, d9
97 @ CHECK-V81M: vminnm.f64 d4, d6, d9 @ encoding: [0x86,0xfe,0x49,0x4b]
120 vrinta.f64 d3, d4
121 @ CHECK-V81M: vrinta.f64 d3, d4 @ encoding: [0xb8,0xfe,0x44,0x3b]
[all …]
H A Dneon-vld-encoding.s12 vld1.16 {d4, d5, d6}, [r3:64]
15 vld1.8 {d1, d2, d3, d4}, [r3]
16 vld1.16 {d4, d5, d6, d7}, [r3:64]
39 vld1.16 {d4, d5, d6}, [r3:64]!
44 vld1.16 {d4, d5, d6}, [r3:64], r6
48 vld1.8 {d1, d2, d3, d4}, [r3]!
49 vld1.16 {d4, d5, d6, d7}, [r3:64]!
53 vld1.8 {d1, d2, d3, d4}, [r3], r8
54 vld1.16 {d4, d5, d6, d7}, [r3:64], r8
67 @ CHECK: vld1.16 {d4, d5, d6}, [r3:64] @ encoding: [0x5f,0x46,0x23,0xf4]
[all …]
/llvm-project/llvm/test/MC/Hexagon/instructions/
H A Dxtype_alu.s63 # CHECK: 70 de d4 c2
73 # CHECK: 30 d4 fe d3
77 # CHECK: 70 d4 fe d3
125 # CHECK: 90 de d4 d3
127 # CHECK: b0 de d4 d3
137 # CHECK: d0 d4 be d3
139 # CHECK: f0 d4 be d3
153 # CHECK: 31 c0 d4 88
169 # CHECK: f0 d4 3e d3
219 # CHECK: 10 d4 7e e8
[all …]
/llvm-project/llvm/test/CodeGen/ARM/
H A Dregalloc-fast-rewrite-implicits.mir15 liveins: $d2, $d4, $d7
18 ; CHECK: liveins: $d2, $d4, $d7
20 ; CHECK-NEXT: renamable $d5 = COPY killed $d4
21 ; CHECK-NEXT: renamable $d4 = COPY killed $d2
23 ; CHECK-NEXT: renamable $d1 = COPY renamable $d4
25 ; CHECK-NEXT: renamable $d3 = COPY killed renamable $d4
27 %0:dpr_vfp2 = COPY $d4
45 liveins: $d2, $d4
48 ; CHECK: liveins: $d2, $d4
50 ; CHECK-NEXT: renamable $d5 = COPY killed $d4
[all …]
H A Dha-alignstack.ll11 define dso_local float @f0_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
21 define dso_local float @f0_1(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
31 define dso_local float @f0_2(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
41 define dso_local float @f1_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
51 define dso_local float @f1_1(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
61 define dso_local float @f1_2(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
71 define dso_local float @f2_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
81 define dso_local float @f2_1(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
91 define dso_local float @f2_2(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5…
101 define dso_local double @g0_0(double %d0, double %d1, double %d2, double %d3, double %d4, double %d…
[all …]
H A Dswift-vldm.ll9 ; CHECK: vldmia r{{[0-9]+}}, {d2, d3, d4}
10 ; CHECK-NOT: vldmia r{{[0-9]+}}, {d1, d2, d3, d4}
12 declare fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
23 %d4 = load double , ptr %addr3
24 ; We are trying to force x[0-3] in registers d1 to d4 so that we can test we
25 ; don't form a "vldmia rX, {d1, d2, d3, d4}".
28 call fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
/llvm-project/clang/test/CodeGenHLSL/BasicFeatures/
H A Dstandard_conversion_sequences.hlsl5 // CHECK: [[d4:%.*]] = alloca <4 x double>
10 // CHECK: store <4 x double> [[vecd4]], ptr [[d4]]
13 vector<double,4> d4 = f3.xyzx;
29 // CHECK: [[d4:%.*]] = alloca <4 x double>
31 // CHECK: store <4 x double> splat (double 3.000000e+00), ptr [[d4]]
32 // CHECK: [[vecd4:%.*]] = load <4 x double>, ptr [[d4]]
37 vector<double,4> d4 = 3.0;
38 vector<float,2> f2 = d4;
56 // CHECK: store <4 x double> splat (double 5.000000e+00), ptr [[d4]]
57 // CHECK: [[vecd4:%.*]] = load <4 x double>, ptr [[d4]]
[all...]
/llvm-project/mlir/test/Dialect/Linalg/
H A Dtransform-pack-greedily.mlir8 // CHECK-DAG: #[[$mk_kkmm:.*]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d0, d3, d4)>
9 // CHECK-DAG: #[[$kn_kknn:.*]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)>
10 // CHECK-DAG: #[[$mn_mmnn:.*]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d2, d4, d5)>
51 // CHECK-DAG: #[[$km_kkmm:.*]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d0, d3, d4)>
52 // CHECK-DAG: #[[$kn_kknn:.*]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d0, d3, d5)>
53 // CHECK-DAG: #[[$mn_mmnn:.*]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d4, d5)>
98 // CHECK-DAG: #[[$mk_kkmm:.*]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d0, d3, d4)>
99 // CHECK-DAG: #[[$kn_kknn:.*]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d0, d3, d5)>
100 // CHECK-DAG: #[[$mn_mmnn:.*]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d4, d5)>
145 // CHECK-DAG: #[[$bmkm2_kkmm:.*]] = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d0, d3, d2, d1,…
[all …]
H A Dblock-pack-matmul-layout.mlir37 // MMT4D-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)>
38 // MMT4D-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d1, d2, d4, d5)>
39 // MMT4D-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)>
59 // MM4D-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d3, d5)>
60 // MM4D-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)>
61 // MM4D-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)>
81 // MTM4D-DAG: #[[$MAP:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d0, d5, d3)>
82 // MTM4D-DAG: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d2, d1, d5, d4)>
83 // MTM4D-DAG: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d3, d4)>
/llvm-project/mlir/include/mlir/Dialect/Linalg/IR/
H A DLinalgNamedStructuredOps.yaml1352 - affine_map<(d0, d1, d2, d3, d4, d5)[s0, s1, s2, s3, s4, s5] -> (d0, d2, d3,
1354 - affine_map<(d0, d1, d2, d3, d4, d5)[s0, s1, s2, s3, s4, s5] -> (d1, d2, d4,
1356 - affine_map<(d0, d1, d2, d3, d4, d5)[s0, s1, s2, s3, s4, s5] -> (d0, d1, d3,
1357 d4)>
1429 - affine_map<(d0, d1, d2, d3, d4, d5, d6)[s0, s1, s2, s3, s4, s5, s6] -> (d0,
1430 d1, d3, d4, d6)>
1431 - affine_map<(d0, d1, d2, d3, d4, d5, d6)[s0, s1, s2, s3, s4, s5, s6] -> (d0,
1433 - affine_map<(d0, d1, d2, d3, d4, d5, d6)[s0, s1, s2, s3, s4, s5, s6] -> (d0,
1434 d1, d2, d4, d
[all...]
/llvm-project/llvm/test/TableGen/
H A Dforeach-eval.td10 def d4;
15 !subst(d4, d0, tmp)))));
21 !subst(d4, d0, tmp))))));
27 def d : D <(d0 d1, d2, d3, d4)>;
49 !subst(d4, d0, tmp)))))]>;
55 !subst(d4, d0, t1))))))>;
58 def j1 : J1< (d1 d2:$dst, (d3 d4:$src1))>;
61 def j2 : J2< [(d1 d2:$dst, (d3 d4:$src1))]>;

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