1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=armv7-apple-ios -run-pass=regallocfast -o - %s | FileCheck %s 3# RUN: llc -mtriple=armv7-apple-ios -passes=regallocfast -o - %s | FileCheck %s 4 5 6# tBX_RET uses an implicit vreg with a sub-register. That implicit use will 7# typically be rewritten as a use of the relevant super-register. Make sure 8# regallocfast is able to process the remaining operands (here, %2) and rewrite 9# them to use physical registers. 10--- 11name: different_vreg 12tracksRegLiveness: true 13body: | 14 bb.0: 15 liveins: $d2, $d4, $d7 16 17 ; CHECK-LABEL: name: different_vreg 18 ; CHECK: liveins: $d2, $d4, $d7 19 ; CHECK-NEXT: {{ $}} 20 ; CHECK-NEXT: renamable $d5 = COPY killed $d4 21 ; CHECK-NEXT: renamable $d4 = COPY killed $d2 22 ; CHECK-NEXT: undef renamable $d0 = COPY renamable $d5, implicit-def $q0_q1 23 ; CHECK-NEXT: renamable $d1 = COPY renamable $d4 24 ; CHECK-NEXT: renamable $d2 = COPY killed renamable $d5 25 ; CHECK-NEXT: renamable $d3 = COPY killed renamable $d4 26 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit killed renamable $d7, implicit killed $q0_q1 27 %0:dpr_vfp2 = COPY $d4 28 %1:dpr_vfp2 = COPY $d2 29 %2:dpr_vfp2 = COPY $d7 30 undef %4.dsub_0:dquad = COPY %0 31 %4.dsub_1:dquad = COPY %1 32 %4.dsub_2:dquad = COPY %0 33 %4.dsub_3:dquad = COPY %1 34 tBX_RET 14, $noreg, implicit %4.dsub_3, implicit %2 35... 36 37 38# tBX_RET uses the same vreg twice, make sure regallocfast is able to allocate a 39# physical register for it and replace both references. 40--- 41name: same_vreg_twice 42tracksRegLiveness: true 43body: | 44 bb.0: 45 liveins: $d2, $d4 46 47 ; CHECK-LABEL: name: same_vreg_twice 48 ; CHECK: liveins: $d2, $d4 49 ; CHECK-NEXT: {{ $}} 50 ; CHECK-NEXT: renamable $d5 = COPY killed $d4 51 ; CHECK-NEXT: renamable $d4 = COPY killed $d2 52 ; CHECK-NEXT: undef renamable $d0 = COPY renamable $d5, implicit-def $q0_q1 53 ; CHECK-NEXT: renamable $d1 = COPY renamable $d4 54 ; CHECK-NEXT: renamable $d2 = COPY killed renamable $d5 55 ; CHECK-NEXT: renamable $d3 = COPY killed renamable $d4 56 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit renamable $d3, implicit killed $q0_q1 57 %0:dpr_vfp2 = COPY $d4 58 %1:dpr_vfp2 = COPY $d2 59 undef %4.dsub_0:dquad = COPY %0 60 %4.dsub_1:dquad = COPY %1 61 %4.dsub_2:dquad = COPY %0 62 %4.dsub_3:dquad = COPY %1 63 tBX_RET 14, $noreg, implicit %4.dsub_1, implicit %4.dsub_3 64... 65 66# tBL partially defines two vregs, which turn out to be dead. Make sure 67# regallocfast allocates a phys reg for both %0 and %1. 68--- 69name: partial_dead 70tracksRegLiveness: true 71body: | 72 bb.0: 73 74 ; CHECK-LABEL: name: partial_dead 75 ; CHECK: tBL 14 /* CC::al */, $noreg, 0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $q0_q1, implicit-def dead $q2_q3 76 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg 77 tBL 14, $noreg, 0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def undef %0.dsub_0:dquad, implicit-def undef %1.dsub_2:dquad 78 tBX_RET 14, $noreg 79... 80