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/freebsd-src/sys/arm/mv/clk/
H A Dperiph.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
53 #define RD4(_clk, offset, val) \ argument
54 CLKDEV_READ_4(clknode_get_device(_clk), offset, val)
67 .clk_def.full_dd.tbg_mux.offset = TBG_SEL, \
72 .clk_def.full_dd.div1.offset = _div1_reg, \
80 .clk_def.full_dd.div2.offset = _div2_reg, \
88 .clk_def.full_dd.clk_mux.offset = CLK_SEL, \
93 .clk_def.full_dd.gate.offset = CLK_DIS, \
109 .clk_def.full_d.tbg_mux.offset = TBG_SEL, \
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/freebsd-src/contrib/llvm-project/llvm/lib/Object/
H A DMachOUniversalWriter.cpp1 //===- MachOUniversalWriter.cpp - MachO universal binary writer---*- C++-*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
106 auto CPU = std::make_pair(MachO::getCPUType(TT), MachO::getCPUSubType(TT)); in getMachoCPUFromTriple() local
107 if (!CPU.first) { in getMachoCPUFromTriple()
108 return CPU.first.takeError(); in getMachoCPUFromTriple()
110 if (!CPU.second) { in getMachoCPUFromTriple()
111 return CPU.second.takeError(); in getMachoCPUFromTriple()
113 return std::make_pair(*CPU.first, *CPU.second); in getMachoCPUFromTriple()
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/freebsd-src/share/man/man9/
H A Ddpcpu.91 .\"-
31 .Nd Kernel Dynamic Per-CPU Memory Allocator
34 .Ss Per-CPU Variable Definition and Declaration
38 .Ss Current CPU Accessor Functions
42 .Ss Named CPU Accessor Functions
43 .Fn DPCPU_ID_PTR "cpu" "name"
44 .Fn DPCPU_ID_GET "cpu" "name"
45 .Fn DPCPU_ID_SET "cpu" "name" "value"
48 instantiates one instance of a global variable with each CPU in the system.
49 Dynamically allocated per-CPU variables are defined using
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/freebsd-src/sys/contrib/device-tree/Bindings/timer/
H A Dqcom,msm-timer.txt5 - compatible : Should at least contain "qcom,msm-timer". More specific
8 "qcom,kpss-timer" - krait subsystem
9 "qcom,scss-timer" - scorpion subsystem
11 - interrupts : Interrupts for the debug timer, the first general purpose
15 - reg : Specifies the base address of the timer registers.
17 - clocks: Reference to the parent clocks, one per output clock. The parents
20 - clock-names: The name of the clocks as free-form strings. They should be in
23 - clock-frequency : The frequency of the debug timer and the general purpose
28 - cpu-offset : per-cpu offset used when the timer is accessed without the
29 CPU remapping facilities. The offset is
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/freebsd-src/share/man/man7/
H A Darch.71 .\" Copyright (c) 2016-2017 The FreeBSD Foundation.
32 .Nd Architecture-specific details
34 Differences between CPU architectures and platforms supported by
40 For full details consult the processor-specific ABI supplement
83 This table shows currently supported CPU architectures along with the first
86 .Bl -column -offset indent "Architecture" "Initial Release"
100 .Bl -column -offse
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/freebsd-src/sys/contrib/device-tree/src/mips/mti/
H A Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
26 cpu@0 {
36 cpu_intc: interrupt-controller {
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/freebsd-src/sys/contrib/device-tree/Bindings/watchdog/
H A Dqcom-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/qcom-wd
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/freebsd-src/sys/contrib/device-tree/src/arm/st/
H A Dstih418-b2264.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "st,stih418-b2264", "st,stih418";
14 stdout-path = &sbc_serial0;
23 cpu@0 {
24 operating-points-v2 = <&cpu_opp_table>;
25 /* u-boot puts hpen in SBC dmem at 0xb8 offset */
26 cpu-release-addr = <0x94100b8>;
28 cpu@1 {
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/freebsd-src/sys/contrib/device-tree/Bindings/arm/hisilicon/controller/
H A Dsysctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wei Xu <xuwei5@hisilicon.com>
19 offset. In addition, the HiP01 system controller has some specific control
23 Hisilicon system controller --> hisilicon,sysctrl
24 HiP01 system controller --> hisilicon,hip01-sysctrl
25 Hi6220 system controller --> hisilicon,hi6220-sysctrl
26 Hi3519 system controller --> hisilicon,hi3519-sysctrl
29 - if:
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/freebsd-src/sys/arm64/arm64/
H A Dgic_v3.c1 /*-
2 * Copyright (c) 2015-2016 The FreeBSD Foundation
56 #include <machine/cpu.h>
112 static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
144 /* MSI/MSI-X */
166 * Driver-specific definitions.
173 /* Destination registers, either Distributor or Re-Distributor */
185 /* be used for MSI/MSI-X interrupts */
187 /* for a MSI/MSI-X interrupt */
199 /* A sequence of init functions for primary (boot) CPU */
220 gic_r_read_4(device_t dev,bus_size_t offset) gic_r_read_4() argument
232 gic_r_read_8(device_t dev,bus_size_t offset) gic_r_read_8() argument
244 gic_r_write_4(device_t dev,bus_size_t offset,uint32_t val) gic_r_write_4() argument
256 gic_r_write_8(device_t dev,bus_size_t offset,uint64_t val) gic_r_write_8() argument
1068 int cpu; gic_v3_bind_intr() local
1103 u_int cpu, irq; gic_v3_init_secondary() local
1221 bus_size_t offset; gic_v3_wait_for_rwp() local
1379 bus_size_t offset; gic_v3_redist_find() local
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H A Dgic_v3_var.h1 /*-
43 bus_size_t offset; member
49 * Re-Distributor region description.
51 * on the #redistributor-regions property in FDT.
54 /* Number of Re-Distributor regions */
57 * Whether to treat each region as a single Re-Distributor page or a
62 /* Per-CPU Re-Distributor data */
72 /* Re-Distributor
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/freebsd-src/share/man/man4/
H A Dhwpmc.41 .\" Copyright (c) 2003-2008 Joseph Koshy
39 .Bd -ragged -offset indent
44 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
54 .Bd -ragged -offset indent
62 .Bd -ragged -offset indent
75 The driver supports multi-processor systems.
89 .Bl -tag -width ".Em Process-scope"
90 .It Em "Process-scope"
92 to a process it is attached to is scheduled on a CPU.
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H A Damdtemp.41 .\"-
33 processor on-die digital thermal sensor
38 .Bd -ragged -offset indent
45 .Bd -literal -offset indent
51 driver provides support for the on-die digital thermal sensor present
61 .Va dev.cpu.%d.temperature
62 in the corresponding CPU device's sysctl tree, displaying the maximum
63 temperature of the two sensors located in each CPU core.
69 .Va dev.cpu.%d.temperature
70 in the corresponding CPU device's sysctl tree, displaying the temperature
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/freebsd-src/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Ddcsr.txt21 - compatible
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
33 - #size-cells
40 - ranges
42 Value type: <prop-encoded-array>
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "fsl,dcsr", "simple-bus";
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/freebsd-src/sys/contrib/device-tree/Bindings/arm/bcm/
H A Dbrcm,bcm63138.txt1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
20 Optional properties for the primary CPU node:
21 - enable-method: should be "brcm,bcm63138"
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H A Dbrcm,brcmstb.txt2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
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/freebsd-src/lib/libsys/
H A Dcpuset.234 .Nd manage CPU affinity sets
57 per-thread mask to bind to a specific CPU or subset of CPUs and memory domains.
66 assignable on a per-process basis.
69 The anonymous set is a further thread-specific refinement on the assigned
83 .Bl -column CPU_LEVEL_CPUSET -offset indent
98 .Bl -column CPU_WHICH_INTRHANDLER -offset indent
112 of '-1' may be used with a
191 .Rv -std
193 In this example, a CPU set mask is configured to limit execution to the first
201 Then, the mask is applied to a new anonymous CPU set associated with the
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/freebsd-src/sys/contrib/device-tree/Bindings/arm/cpu-enable-method/
H A Dal,alpine-smp2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
12 Compatible CPUs: "arm,cortex-a15"
17 "al,alpine-cpu-resum
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/freebsd-src/sys/contrib/device-tree/Bindings/arm/marvell/
H A Dap80x-system-controller.txt6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
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/freebsd-src/sys/powerpc/powerpc/
H A Dplatform.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
53 #include <machine/cpu.h>
86 if ((r1->mr_start + r1->mr_size) < r2->mr_start || in memr_overlap()
87 (r2->mr_start + r2->mr_size) < r1->mr_start) in memr_overlap()
97 end = uqmax(to->mr_start + to->mr_size, from->mr_start + from->mr_size); in memr_merge()
98 to->mr_start = uqmin(from->mr_start, to->mr_start); in memr_merge()
99 to->mr_size = end - to->mr_start; in memr_merge()
112 if (regiona->mr_start < regionb->mr_start) in mr_cmp()
113 return (-1); in mr_cmp()
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/freebsd-src/sys/contrib/alpine-hal/
H A Dal_hal_plat_services.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
42 * - Registers read/write
43 * - Assertions
44 * - Memory barriers
45 * - Endianness conversions
73 bus_size_t offset);
76 bus_size_t offset);
79 bus_size_t offset);
82 bus_size_t offset, uint8_t value);
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/freebsd-src/contrib/bearssl/T0/
H A DWordData.cs32 int offset; field in WordData
36 ConstData blob, int offset) in WordData() argument
40 this.offset = offset; in WordData()
45 string baseBlobName, int offset) in WordData() argument
49 this.offset = offset; in WordData()
66 "data word '{0}' based on non-data word '{1}'", in Resolve()
71 offset += wd.offset; in Resolve()
75 internal override void Run(CPU cpu) in Run() argument
78 cpu.Push(new TValue(offset, new TPointerBlob(blob))); in Run()
93 dst.Add(new CodeElementUIntInt(1, blob.Address + offset)); in GenerateCodeElements()
/freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
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/freebsd-src/sys/cddl/contrib/opensolaris/uts/common/sys/
H A Ddtrace_impl.h152 size_t dth_nextoffs; /* offset of next in probe */
153 size_t dth_prevoffs; /* offset of prev in probe */
154 size_t dth_stroffs; /* offset of str in probe */
172 * +-------
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/freebsd-src/sys/contrib/device-tree/src/arm64/apm/
H A Dapm-storm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cell
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