Lines Matching +full:cpu +full:- +full:offset
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
53 #define RD4(_clk, offset, val) \ argument
54 CLKDEV_READ_4(clknode_get_device(_clk), offset, val)
67 .clk_def.full_dd.tbg_mux.offset = TBG_SEL, \
72 .clk_def.full_dd.div1.offset = _div1_reg, \
80 .clk_def.full_dd.div2.offset = _div2_reg, \
88 .clk_def.full_dd.clk_mux.offset = CLK_SEL, \
93 .clk_def.full_dd.gate.offset = CLK_DIS, \
109 .clk_def.full_d.tbg_mux.offset = TBG_SEL, \
114 .clk_def.full_d.div.offset = _div1_reg, \
122 .clk_def.full_d.clk_mux.offset = CLK_SEL, \
127 .clk_def.full_d.gate.offset = CLK_DIS, \
141 .clk_def.cpu.tbg_mux.clkdef.name = _tbg_mux_name, \
142 .clk_def.cpu.tbg_mux.offset = TBG_SEL, \
143 .clk_def.cpu.tbg_mux.shift = _tbg_mux_shift, \
144 .clk_def.cpu.tbg_mux.width = 0x2, \
145 .clk_def.cpu.tbg_mux.mux_flags = 0x0, \
146 .clk_def.cpu.div.clkdef.name = _div1_name, \
147 .clk_def.cpu.div.offset = _div1_reg, \
148 .clk_def.cpu.div.i_shift = _div1_shift, \
149 .clk_def.cpu.div.i_width = 0x3, \
150 .clk_def.cpu.div.f_shift = 0x0, \
151 .clk_def.cpu.div.f_width = 0x0, \
152 .clk_def.cpu.div.div_flags = 0x0, \
153 .clk_def.cpu.div.div_table = _div_table, \
154 .clk_def.cpu.clk_mux.clkdef.name = _name, \
155 .clk_def.cpu.clk_mux.offset = CLK_SEL, \
156 .clk_def.cpu.clk_mux.shift = _clk_mux_shift, \
157 .clk_def.cpu.clk_mux.width = 0x1, \
158 .clk_def.cpu.clk_mux.mux_flags = 0x0, \
169 .clk_def.gate.gate.offset = CLK_DIS, \
185 .clk_def.mdd.tbg_mux.offset = TBG_SEL, \
190 .clk_def.mdd.div1.offset = _div1_reg, \
198 .clk_def.mdd.div2.offset = _div2_reg, \
206 .clk_def.mdd.clk_mux.offset = CLK_SEL, \
220 .clk_def.mux_gate.mux.offset = TBG_SEL, \
225 .clk_def.mux_gate.gate.offset = CLK_DIS, \
241 .clk_def.mux_gate_fixed.mux.offset = TBG_SEL, \
246 .clk_def.mux_gate_fixed.gate.offset = CLK_DIS, \
263 .clk_def.fixed.mux.offset = TBG_SEL, \
268 .clk_def.fixed.gate.offset = CLK_DIS, \
351 /* CPU clock */
375 struct a37x0_periph_clk_cpu_def cpu; member