| /freebsd-src/sys/contrib/device-tree/Bindings/power/reset/ |
| H A D | keystone-reset.txt | 3 This node is intended to allow SoC reset in case of software reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
26 - ti,soft-reset: Boolean option indicating soft reset.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
30 to WDT driver, it's just needed to enable a SoC related
31 reset that's triggered by one of WDTs. The list is
33 begins from 0 to 3, as keystone can contain up to 4 SoC
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| /freebsd-src/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
41 Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
45 Some requirements for using fsl,imx-pinctrl binding:
47 what pinmux functions this SoC supports.
[all …]
|
| H A D | brcm,iproc-gpio.txt | 5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
23 - reg:
[all …]
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| /freebsd-src/sys/contrib/device-tree/Bindings/ptp/ |
| H A D | brcm,ptp-dte.txt | 4 - compatible: should contain the core compatibility string
5 and the SoC compatibility string. The SoC
6 compatibility string is to handle SoC specific
9 "brcm,ptp-dte"
10 SoC compatibility strings:
11 "brcm,iproc-ptp-dte" - for iproc based SoC's
12 - reg: address and length of the DTE block's NCO registers
16 ptp: ptp-dte@180af650 {
17 compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
|
| /freebsd-src/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | mpc5121-psc.txt | 4 ----------------
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
16 Supported <soc>s: mpc5121, mpc5125
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
[all …]
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| /freebsd-src/sys/contrib/device-tree/Bindings/edac/ |
| H A D | apm-xgene-edac.txt | 1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
[all …]
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| /freebsd-src/sys/contrib/device-tree/Bindings/dma/ |
| H A D | fsl-edma.txt | 3 The eDMA channels have multiplex capability by programmble memory-mapped
10 - compatible :
11 - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
12 - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp
13 - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the
14 LS1028A SoC.
15 - reg : Specifies base physical address(s) and size of the eDMA registers.
16 The 1st region is eDMA control register's address and size.
18 control register's address and size.
19 - interrupts : A list of interrupt-specifiers, one for each entry in
[all …]
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| /freebsd-src/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | s3c6400.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S3C6400 SoC device tree source
7 * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400
12 * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional
23 valid-mask = <0xfffffe1f>;
24 valid-wakeup-mask = <0x00200004>;
28 valid-mask = <0xffffffff>;
29 valid-wakeup-mask = <0x53020000>;
32 &soc {
33 clocks: clock-controller@7e00f000 {
[all …]
|
| H A D | s3c6410.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S3C6410 SoC device tree source
7 * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410
12 * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional
27 valid-mask = <0xffffff7f>;
28 valid-wakeup-mask = <0x00200004>;
32 valid-mask = <0xffffffff>;
33 valid-wakeup-mask = <0x53020000>;
36 &soc {
37 clocks: clock-controller@7e00f000 {
[all …]
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| /freebsd-src/sys/contrib/device-tree/Bindings/arm/keystone/ |
| H A D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...] |
| H A D | ti,sci.txt | 1 Texas Instruments System Control Interface (TI-SCI) Message Protocol
2 --------------------------------------------------------------------
4 Texas Instrument's processors including those belonging to Keystone generation
6 management of the System on Chip (SoC) system. These include various system
9 An example of such an SoC is K2G, which contains the system control hardware
16 TI-SCI controller Device Node:
19 The TI-SCI node describes the Texas Instrument's System Controller entity node.
22 functionality as may be required for the SoC. This hierarchy also describes the
23 relationship between the TI-SCI parent node to the child node.
26 -------------------
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|
| /freebsd-src/sys/contrib/device-tree/Bindings/pwm/ |
| H A D | pwm-mediatek.txt | 4 - compatible: should be "mediatek,<name>-pwm":
5 - "mediatek,mt2712-pwm": found on mt2712 SoC.
6 - "mediatek,mt6795-pwm": found on mt6795 SoC.
7 - "mediatek,mt7622-pwm": found on mt7622 SoC.
8 - "mediatek,mt7623-pwm": found on mt7623 SoC.
9 - "mediatek,mt7628-pwm": found on mt7628 SoC.
10 - "mediatek,mt7629-pwm": found on mt7629 SoC.
11 - "mediatek,mt8183-pwm": found on mt8183 SoC.
12 - "mediatek,mt8195-pwm", "mediatek,mt8183-pwm": found on mt8195 SoC.
13 - "mediatek,mt8365-pwm": found on mt8365 SoC.
[all …]
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| /freebsd-src/sys/contrib/device-tree/Bindings/usb/ |
| H A D | mediatek,mtk-xhci.txt | 3 The device node for Mediatek SOC USB3.0 host controller
6 the second one supports dual-role mode, and the host is based on xHCI
11 ------------------------------------------------------------------------
14 - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci",
15 soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
16 "mediatek,mtk-xhci" compatible string, you need SoC specific ones in
18 - "mediatek,mt8173-xhci"
19 - reg : specifies physical base address and size of the registers
20 - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
21 - interrupts : interrupt used by the controller
[all …]
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| /freebsd-src/sys/contrib/device-tree/Bindings/hwmon/ |
| H A D | amd,sbrmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Sideband Remote Management Interface (SB-RMI) compliant
9 AMD SoC power device.
12 - Akshay Gupta <Akshay.Gupta@amd.com>
15 SB Remote Management Interface (SB-RMI) is an SMBus compatible
16 interface that reports AMD SoC's Power (normalized Power) using,
17 Mailbox Service Request and resembles a typical 8-pin remote power
18 sensor's I2C interface to BMC. The power attributes in hwmon
[all …]
|
| H A D | amd,sbtsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Sideband interface Temperature Sensor Interface (SB-TSI) compliant
9 AMD SoC temperature device
12 - Kun Yi <kunyi@google.com>
13 - Supreeth Venkatesh <supreeth.venkatesh@amd.com>
16 SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
17 interface that reports AMD SoC's Ttcl (normalized temperature),
18 and resembles a typical 8-pin remote temperature sensor's I2C interface
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/clock/ |
| H A D | microchip,mpfs-ccc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
10 - Conor Dooley <conor.dooley@microchip.com>
13 Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
15 the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
20 const: microchip,mpfs-ccc
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | 8xxx_gpio.txt | 3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
14 module's interrupt.
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
22 - compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
23 for 83xx, "fsl,mpc8572-gpio" for 85xx, or
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/net/dsa/ |
| H A D | mediatek,mt7530.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...] |
| /freebsd-src/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm,realview.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...] |
| /freebsd-src/sys/arm/nvidia/ |
| H A D | tegra_soctherm.c | 1 /*-
30 * Calibration data and algo are taken from Linux, because this part of SoC
52 #include <dt-bindings/thermal/tegra124-soctherm.h>
55 /* Per sensors registers - base is 0x0c0*/
131 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
132 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
176 struct soctherm_soc *soc; member
208 .fuse_corr_beta = -6266900,
212 .id = -
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| /freebsd-src/sys/contrib/device-tree/Bindings/slimbus/ |
| H A D | slim-qcom-ctrl.txt | 7 - #address-cells - refer to Documentation/devicetree/bindings/slimbus/bus.txt
8 - #size-cells - refer to Documentation/devicetree/bindings/slimbus/bus.txt
10 - reg : Offset and length of the register region(s) for the device
11 - reg-names : Register region name(s) referenced in reg above
14 "slew": required for "qcom,apq8064-slim" SOC.
15 - compatible : should be "qcom,<SOC-NAME>-slim" for SOC specific compatible
17 - interrupts : Interrupt number used by this controller
18 - clocks : Interface and core clocks used by this SLIMbus controller
19 - clock-names : Required clock-name entries are:
21 "core" : Interrupt for controller core's BAM
[all …]
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| /freebsd-src/sys/contrib/device-tree/Bindings/soc/ti/ |
| H A D | wkup-m3-ipc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dave Gerlach <d-gerlach@ti.com>
11 - Drew Fustini <dfustini@baylibre.com>
14 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
17 C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
19 present in the SoC's control module and a mailbox. The wkup_m3_ipc exposes an
20 API to allow the SoC PM code to execute specific PM tasks.
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/sound/ |
| H A D | uniphier,aio.txt | 1 Socionext UniPhier SoC audio driver
3 The Socionext UniPhier audio subsystem consists of I2S and S/PDIF blocks in
7 - compatible : should be one of the following:
8 "socionext,uniphier-ld11-aio"
9 "socionext,uniphier-ld20-aio"
10 "socionext,uniphier-pxs2-aio"
11 - reg : offset and length of the register set for the device.
12 - interrupts : should contain I2S or S/PDIF interrupt.
13 - pinctrl-names : should be "default".
14 - pinctrl-0 : defined I2S signal pins for an external codec chip.
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | samsung-sdhci.txt | 1 * Samsung's SDHCI Controller device tree bindings
3 Samsung's SDHCI controller is used as a connectivity interface with external
8 Required SoC Specific Properties:
9 - compatible: should be one of the following
10 - "samsung,s3c6410-sdhci": For controllers compatible with s3c6410 sdhci
12 - "samsung,exynos4210-sdhci": For controllers compatible with Exynos4 sdhci
16 - pinctrl-0: Should specify pin control groups used for this controller.
17 - pinctrl-names: Should contain only one value - "default".
21 compatible = "samsung,exynos4210-sdhci";
24 bus-width = <4>;
[all …]
|
| /freebsd-src/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-mtk-nor.txt | 4 - compatible: For mt8173, compatible should be "mediatek,mt8173-nor",
5 and it's the fallback compatible for other Soc.
6 For every other SoC, should contain both the SoC-specific compatible
7 string and "mediatek,mt8173-nor".
9 "mediatek,mt2701-nor", "mediatek,mt8173-nor"
10 "mediatek,mt2712-nor", "mediatek,mt8173-nor"
11 "mediatek,mt7622-nor", "mediatek,mt8173-nor"
12 "mediatek,mt7623-nor", "mediatek,mt8173-nor"
13 "mediatek,mt7629-nor", "mediatek,mt8173-nor"
14 "mediatek,mt8173-nor"
[all …]
|