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/freebsd-src/contrib/file/magic/Magdir/
H A Dacorn7 # RISC OS Chunk File Format
8 # From RISC OS Programmer's Reference Manual, Appendix D
10 0 lelong 0xc3cbc6c5 RISC OS Chunk data
14 # RISC OS AIF, contains "SWI OS_Exit" at offset 16.
15 16 lelong 0xef000011 RISC OS AIF executable
17 # RISC OS Draw files
18 # From RISC OS Programmer's Reference Manual, Appendix E
19 0 string Draw RISC OS Draw file data
21 # RISC OS new format font files
22 # From RISC O
[all...]
H A Delf42 0 name elf-pa-risc
113 >18 leshort 15 PA-RISC,
116 >>>36 use elf-pa-risc
119 >>>48 use elf-pa-risc
152 >18 leshort 45 Argonaut RISC Core, Argonaut Technologies Inc.,
216 >18 leshort 109 Arca RISC,
226 >18 leshort 119 Freescale RISC core,
231 >18 leshort 135 Sunplus S+core7 RISC,
247 >18 leshort 167 Andes embedded RISC,
251 >18 leshort 171 M2000 Reconfigurable RISC,
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/timer/
H A Driscv,timer.yaml7 title: RISC-V timer
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
/freebsd-src/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml7 title: RISC-V ISA extensions
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
37 supported by the hart. These are documented in the RISC-V
134 added by other RISC-V extensions in H/S/VS/U/VU modes and as
216 in version 1.0 of RISC-V Cryptography Extensions Volume I
222 in version 1.0 of RISC-V Cryptography Extensions Volume I
228 in version 1.0 of RISC-V Cryptography Extensions Volume I
296 in version 1.0 of RISC
[all...]
H A Dcpus.yaml7 title: RISC-V CPUs
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
62 Identifies that the hart uses the RISC-V instruction set
68 this hart. These values originate from the RISC-V Privileged
98 # RISC-V has multiple properties for cache op block sizes as the sizes
101 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
/freebsd-src/share/i18n/csmapper/MISC/
H A DRISCOS-LATIN1%UCS.src14 # The charset used on RISC OS ('Acorn RISC OS'). The same as Latin-1,
20 # Now the RISC OS specific characters. This is from RISC OS 3.11. In
21 # earlier versions of RISC OS, some of these were used for drawing
27 # in Homerton, one of the outline fonts that comes with RISC OS. The
29 # supplied by EFF, a third-party supplier of RISC OS outline fonts.
/freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
18 All RISC-V systems that conform to the supervisor ISA specification are
29 RISC-V supervisor ISA manual, with only the following three interrupts being
H A Dsifive,plic-1.0.0.yaml11 SiFive SoCs and other RISC-V SoCs include an implementation of the
13 the RISC-V Privileged Architecture specification. The PLIC connects all
30 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
38 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
/freebsd-src/contrib/llvm-project/llvm/include/llvm/Support/
H A DRISCVISAInfo.h
H A DRISCVAttributes.h9 // This file contains enumerations for RISCV attributes as defined in RISC-V
12 // RISC-V ELF psABI specification
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.h1 //===-- RISCVMCTargetDesc.h - RISC-V Target Descriptions --------*- C++ -*-===//
9 // This file provides RISC-V specific target descriptions.
55 // Defines symbolic names for RISC-V registers.
59 // Defines symbolic names for RISC-V instructions.
/freebsd-src/sys/crypto/des/
H A Ddes_ecb.c66 const char *ptr,*unroll,*risc,*size; in des_options() local
75 risc="risc1"; in des_options()
78 risc="risc2"; in des_options()
81 risc="cisc"; in des_options()
92 sprintf(buf,"des(%s,%s,%s,%s)",ptr,risc,unroll,size); in des_options()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCV.td1 //===-- RISCV.td - Describe the RISC-V Target Machine ------*- tablegen -*-===//
12 // RISC-V subtarget features and instruction predicates.
18 // RISC-V profiles supported.
40 // RISC-V macro fusions.
46 // RISC-V Scheduling Models
58 // RISC-V processors supported.
64 // Define the RISC-V target.
H A DRISCVISelDAGToDAG.h1 //===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISC-V -----===//
9 // This file defines an instruction selector for the RISC-V target.
21 // RISC-V specific code to select RISC-V machine instructions for
166 // Return the RISC-V condition code that matches the given DAG integer in getRISCVCCForIntCC()
167 // condition code. The CondCode must be one of those supported by the RISC-V in getRISCVCCForIntCC()
H A DRISCVCallingConv.td1 //===-- RISCVCallingConv.td - Calling Conventions RISC-V ---*- tablegen -*-===//
9 // This describes the calling conventions for the RISC-V architecture.
13 // The RISC-V calling convention is handled with custom code in
H A DRISCVFrameLowering.h1 //===-- RISCVFrameLowering.h - Define frame lowering for RISC-V -*- C++ -*-===//
9 // This class implements RISC-V specific bits of TargetFrameLowering class.
78 // We don't support putting RISC-V Vector objects into the pre-allocated
H A DRISCVInsertReadWriteCSR.cpp1 //===-- RISCVInsertReadWriteCSR.cpp - Insert Read/Write of RISC-V CSR -----===//
9 // of the RISC-V instructions.
24 #define RISCV_INSERT_READ_WRITE_CSR_NAME "RISC-V Insert Read/Write CSR Pass"
H A DRISCVRedundantCopyElimination.cpp1 //=- RISCVRedundantCopyElimination.cpp - Remove useless copy for RISC-V -----=//
22 // do on RISC-V since branches can't have immediates.
59 return "RISC-V Redundant Copy Elimination"; in getPassName()
71 "RISC-V Redundant Copy Elimination", false, false)
H A DRISCVInstrGISel.td1 //===-- RISCVInstrGISel.td - RISC-V GISel target pseudos ----*- tablegen -*-===//
10 // RISC-V GlobalISel target pseudo instruction definitions. This is kept
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/TargetInfo/
H A DRISCVTargetInfo.cpp1 //===-- RISCVTargetInfo.cpp - RISC-V Target Implementation ----------------===//
25 getTheRISCV32Target(), "riscv32", "32-bit RISC-V", "RISCV"); in LLVMInitializeRISCVTargetInfo()
27 getTheRISCV64Target(), "riscv64", "64-bit RISC-V", "RISCV"); in LLVMInitializeRISCVTargetInfo()
/freebsd-src/contrib/llvm-project/clang/include/clang/Sema/
H A DRISCVIntrinsicManager.h1 //===- RISCVIntrinsicManager.h - RISC-V Intrinsic Handler -------*- C++ -*-===//
9 // This file defines the RISCVIntrinsicManager, which handles RISC-V vector
33 // Create RISC-V intrinsic and insert into symbol table and return true if
/freebsd-src/contrib/llvm-project/llvm/utils/TableGen/
H A DRISCVTargetDefEmitter.cpp1 //===- RISCVTargetDefEmitter.cpp - Generate lists of RISC-V CPUs ----------===//
10 // and RISCVISAInfo.cpp to parse the RISC-V CPUs and extensions.
92 // in RISC-V ISA specification (version 20191213) 'Chapter 27. ISA Extension
257 "RISC-V");
/freebsd-src/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfoPOSIX_riscv64.cpp59 // RISC-V64 general purpose registers.
76 // RISC-V64 floating point registers.
93 // Register sets for RISC-V64.
/freebsd-src/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsRISCVVector.def1 //==- BuiltinsRISCVVector.def - RISC-V Vector Builtin Database ---*- C++ -*-==//
9 // This file defines the RISC-V-specific builtin function database. Users of
/freebsd-src/sys/riscv/riscv/
H A Dtimer.c36 * RISC-V Timer
72 .tc_name = "RISC-V Timecounter",
187 device_set_desc(dev, "RISC-V Timer"); in riscv_timer_probe()
245 sc->et.et_name = "RISC-V Eventtimer"; in riscv_timer_attach()

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