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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZb.td254 : RVInstIUnary<imm12, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
260 : RVInstIShift<imm11_7, funct3, opcode, (outs GPR:$rd),
261 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
267 : RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
268 (ins GPR:$rs1, uimm5:$shamt), opcodestr,
460 def : InstAlias<"zext.w $rd, $rs", (ADD_UW GPR:$rd, GPR:$rs, X0)>;
465 (RORI GPR:$rd, GPR
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H A DRISCVInstrInfoXTHead.td72 (ins VR:$vd, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
82 : RVInstRBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
83 (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
93 : RVInstIShift<funct5, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
94 (ins GPR:$rs1, uimmlog2xlen:$shamt),
98 : RVInstIBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
99 (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
109 (outs GPR:$rd), (ins GPR
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H A DRISCVGISel.td86 def : Pat<(XLenVT (sub GPR:$rs1, simm12Plus1:$imm)),
87 (ADDI GPR:$rs1, (NegImm simm12Plus1:$imm))>;
90 def : Pat<(i32 (sub GPR:$rs1, simm12Plus1i32:$imm)),
91 (ADDIW GPR:$rs1, (i64 (NegImm $imm)))>;
93 def : Pat<(i32 (shl GPR:$rs1, (i32 GPR:$rs2))), (SLLW GPR:$rs1, GPR:$rs2)>;
94 def : Pat<(i32 (sra GPR:$rs1, (i32 GPR:$rs2))), (SRAW GPR:$rs1, GPR:$rs2)>;
95 def : Pat<(i32 (srl GPR:$rs1, (i32 GPR:$rs2))), (SRLW GPR:$rs1, GPR:$rs2)>;
102 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), simm12:$imm12)),
103 (SLTIU GPR:$rs1, simm12:$imm12)>;
104 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
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H A DRISCVInstrInfoA.td21 (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1),
36 (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
49 (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
129 def : StPat<atomic_store_8, SB, GPR, XLenVT>;
130 def : StPat<atomic_store_16, SH, GPR, XLenVT>;
131 def : StPat<atomic_store_32, SW, GPR, XLenVT>;
136 def : StPat<atomic_store_64, SD, GPR, i64>;
192 class PseudoAMO : Pseudo<(outs GPR
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H A DRISCVInstrInfoZa.td59 defm AMOCAS_W : AMO_cas_aq_rl<0b00101, 0b010, "amocas.w", GPR>;
67 defm AMOCAS_D_RV64 : AMO_cas_aq_rl<0b00101, 0b011, "amocas.d", GPR>;
74 def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (vt GPR:$addr),
75 (vt GPR:$cmp),
76 (vt GPR:$new)),
77 (!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
78 def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") (vt GPR:$addr),
79 (vt GPR
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H A DRISCVInstrInfo.td119 // A parse method for (${gpr}) or 0(${gpr}), where the 0 is be silently ignored.
131 def GPRMemZeroOffset : MemOperand<GPR> {
136 def GPRMem : MemOperand<GPR>;
509 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
518 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPRMem:$rs1, simm12:$imm12),
522 : RVInstR<funct7, 0b100, OPC_SYSTEM, (outs GPR:$rd),
534 (ins GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
539 (ins GPR
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H A DRISCVInstrInfoXVentana.td20 : RVInstR<0b0000000, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
21 (ins GPR:$rs1, GPR:$rs2), opcodestr,
32 def : Pat<(i64 (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
33 (VT_MASKC GPR:$rs1, GPR:$rc)>;
34 def : Pat<(i64 (riscv_czero_nez GPR:$rs1, GPR:$rc)),
35 (VT_MASKCN GPR:$rs1, GPR:$rc)>;
37 def : Pat<(i64 (riscv_czero_eqz GPR:$rs1, (riscv_setne (i64 GPR:$rc)))),
38 (VT_MASKC GPR:$rs1, GPR:$rc)>;
39 def : Pat<(i64 (riscv_czero_eqz GPR:$rs1, (riscv_seteq (i64 GPR:$rc)))),
40 (VT_MASKCN GPR:$rs1, GPR:$rc)>;
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H A DRISCVInstrInfoXCV.td26 : CVInstBitManipRII<funct2, funct3, (outs GPR:$rd),
27 (ins GPR:$rs1, i3type:$is3, uimm5:$is2),
31 : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
32 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
35 : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
36 (ins GPR:$rs1), opcodestr, "$rd, $rs1"> {
54 def CV_INSERT : CVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),
55 (ins GPR:$rd, GPR
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H A DRISCVInstrInfoZicond.td37 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
38 (CZERO_EQZ GPR:$rs1, GPR:$rc)>;
39 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)),
40 (CZERO_NEZ GPR:$rs1, GPR:$rc)>;
42 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
43 (CZERO_EQZ GPR:$rs1, GPR:$rc)>;
44 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
45 (CZERO_NEZ GPR:$rs1, GPR:$rc)>;
46 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
47 (CZERO_NEZ GPR:$rs1, GPR:$rc)>;
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H A DRISCVInstrInfoD.td50 def FPR64INX : RegisterOperand<GPR> {
131 defm FCLASS_D : FPUnaryOp_r_m<0b1110001, 0b00000, 0b001, Ext, GPR, Ext.PrimaryTy,
136 defm FCVT_W_D : FPUnaryOp_r_frm_m<0b1100001, 0b00000, Ext, GPR, Ext.PrimaryTy,
141 defm FCVT_WU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00001, Ext, GPR, Ext.PrimaryTy,
145 defm FCVT_D_W : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00000, Ext, Ext.PrimaryTy, GPR,
149 defm FCVT_D_WU : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00001, Ext, Ext.PrimaryTy, GPR,
155 defm FCVT_L_D : FPUnaryOp_r_frm_m<0b1100001, 0b00010, Ext, GPR, Ext.PrimaryTy,
159 defm FCVT_LU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00011, Ext, GPR, Ext.PrimaryTy,
163 defm FCVT_D_L : FPUnaryOp_r_frm_m<0b1101001, 0b00010, Ext, Ext.PrimaryTy, GPR,
167 defm FCVT_D_LU : FPUnaryOp_r_frm_m<0b1101001, 0b00011, Ext, Ext.PrimaryTy, GPR,
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H A DRISCVInstrInfoF.td271 : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd),
340 defm FCVT_W_S : FPUnaryOp_r_frm_m<0b1100000, 0b00000, Ext, GPR, Ext.PrimaryTy,
345 defm FCVT_WU_S : FPUnaryOp_r_frm_m<0b1100000, 0b00001, Ext, GPR, Ext.PrimaryTy,
356 defm FCLASS_S : FPUnaryOp_r_m<0b1110000, 0b00000, 0b001, Ext, GPR, Ext.PrimaryTy,
360 defm FCVT_S_W : FPUnaryOp_r_frm_m<0b1101000, 0b00000, Ext, Ext.PrimaryTy, GPR,
364 defm FCVT_S_WU : FPUnaryOp_r_frm_m<0b1101000, 0b00001, Ext, Ext.PrimaryTy, GPR,
368 defm FCVT_L_S : FPUnaryOp_r_frm_m<0b1100000, 0b00010, Ext, GPR, Ext.PrimaryTy,
372 defm FCVT_LU_S : FPUnaryOp_r_frm_m<0b1100000, 0b00011, Ext, GPR, Ext.PrimaryTy,
376 defm FCVT_S_L : FPUnaryOp_r_frm_m<0b1101000, 0b00010, Ext, Ext.PrimaryTy, GPR,
380 defm FCVT_S_LU : FPUnaryOp_r_frm_m<0b1101000, 0b00011, Ext, Ext.PrimaryTy, GPR,
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H A DRISCVInstrInfoVVLPatterns.td651 (mask_type V0), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
678 GPR:$vl, sew, TAIL_AGNOSTIC)>;
711 GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
731 GPR:$vl, sew, TAIL_AGNOSTIC)>;
744 GPR:$vl, sew, TU_MU)>;
766 (mask_type V0), GPR:$vl, sew, TU_MU)>;
793 GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
809 GPR:$vl, log2sew, TU_MU)>;
839 (mask_type V0), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
867 GPR
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H A DRISCVInstrInfoM.td95 def : Pat<(and (riscv_divuw (assertzexti32 GPR:$rs1),
96 (assertzexti32 GPR:$rs2)), 0xffffffff),
97 (DIVU GPR:$rs1, GPR:$rs2)>;
98 def : Pat<(and (riscv_remuw (assertzexti32 GPR:$rs1),
99 (assertzexti32 GPR:$rs2)), 0xffffffff),
100 (REMU GPR:$rs1, GPR:$rs2)>;
105 def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR
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H A DRISCVInstrInfoZfh.td122 defm FCVT_W_H : FPUnaryOp_r_frm_m<0b1100010, 0b00000, Ext, GPR, Ext.PrimaryTy,
127 defm FCVT_WU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00001, Ext, GPR, Ext.PrimaryTy,
131 defm FCVT_H_W : FPUnaryOp_r_frm_m<0b1101010, 0b00000, Ext, Ext.PrimaryTy, GPR,
135 defm FCVT_H_WU : FPUnaryOp_r_frm_m<0b1101010, 0b00001, Ext, Ext.PrimaryTy, GPR,
152 def FMV_X_H : FPUnaryOp_r<0b1110010, 0b00000, 0b000, GPR, FPR16, "fmv.x.h">,
156 def FMV_H_X : FPUnaryOp_r<0b1111010, 0b00000, 0b000, FPR16, GPR, "fmv.h.x">,
168 defm FCLASS_H : FPUnaryOp_r_m<0b1110010, 0b00000, 0b001, Ext, GPR, Ext.PrimaryTy,
172 defm FCVT_L_H : FPUnaryOp_r_frm_m<0b1100010, 0b00010, Ext, GPR, Ext.PrimaryTy,
176 defm FCVT_LU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00011, Ext, GPR, Ext.PrimaryTy,
180 defm FCVT_H_L : FPUnaryOp_r_frm_m<0b1101010, 0b00010, Ext, Ext.PrimaryTy, GPR,
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td213 def GPRMemAtomic : RegisterOperand<GPR> {
635 : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), "$rd, $rj, $rk">;
637 : Fmt2R<op, (outs GPR:$rd), (ins GPR:$rj), "$rd, $rj">;
640 : Fmt3RI2<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm2),
643 : Fmt3RI3<op, (outs GPR
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H A DLoongArchLBTInstrFormats.td28 : LAInst<(outs), (ins GPR:$rj),
39 : LAInst<(outs), (ins GPR:$rj, uimm3:$imm3),
52 : LAInst<(outs), (ins GPR:$rj, uimm4:$imm4),
65 : LAInst<(outs GPR:$rd), (ins uimm4:$imm4),
78 : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5),
91 : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5, uimm4:$imm4),
106 : LAInst<(outs GPR:$rd), (ins uimm5:$imm5, uimm8:$imm8),
121 : LAInst<(outs), (ins GPR:$rj, uimm6:$imm6),
134 : LAInst<(outs GPR:$rd), (ins uimm8:$imm8),
147 : LAInst<(outs), (ins GPR:$rj, GPR:$rk),
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td443 let MIOperandInfo = (ops GPR, uimm5);
528 [(set GPR:$rz, (or GPR:$rx, uimm16:$imm16))]>;
533 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
534 [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
536 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
537 [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
539 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
540 [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
542 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
543 [(set GPR:$rz, (rotl GPR:$rx, uimm5:$imm5))]>;
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H A DCSKYInstrInfoF2.td61 def f2FLD_S : F2_LDST_S<0b0, "fld", (outs FPR32Op:$vrz), (ins GPR:$rx, uimm8_2:$imm8)>;
63 def f2FLD_D : F2_LDST_D<0b0, "fld", (outs FPR64Op:$vrz), (ins GPR:$rx, uimm8_2:$imm8)>;
66 def f2FST_S : F2_LDST_S<0b1, "fst", (outs), (ins FPR32Op:$vrz, GPR:$rx, uimm8_2:$imm8)>;
68 def f2FST_D : F2_LDST_D<0b1, "fst", (outs), (ins FPR64Op:$vrz, GPR:$rx, uimm8_2:$imm8)>;
72 def f2FSTM_S : F2_LDSTM_S<0b1, 0, "fstm", (outs), (ins GPR:$rx, regseq_f2:$regs, variable_ops)>;
74 def f2FSTM_D : F2_LDSTM_D<0b1, 0, "fstm", (outs), (ins GPR:$rx, regseq_d2:$regs, variable_ops)>;
76 …def f2FSTMU_S : F2_LDSTM_S<0b1, 0b100, "fstmu", (outs), (ins GPR:$rx, regseq_f2:$regs, variable_op…
78 …def f2FSTMU_D : F2_LDSTM_D<0b1, 0b100, "fstmu", (outs), (ins GPR:$rx, regseq_d2:$regs, variable_op…
82 def f2FLDM_S : F2_LDSTM_S<0b0, 0, "fldm", (outs), (ins GPR:$rx, regseq_f2:$regs, variable_ops)>;
84 def f2FLDM_D : F2_LDSTM_D<0b0, 0, "fldm", (outs), (ins GPR:$rx, regseq_d2:$regs, variable_ops)>;
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H A DCSKYInstrFormats.td81 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
94 : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), (ins ImmType:$imm16),
96 [(set GPR:$rz, ImmType:$imm16)]> {
110 : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), ins,
132 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx),
145 (ins GPR:$rx, operand:$imm2),
172 (ins GPR:$rx, operand:$imm16), !strconcat(op, "\t$rx, $imm16"), []> {
184 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx, operand:$imm16),
198 : CSKY32Inst<AddrModeNone, 0x39, (outs GPR:$rz),
199 (ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"),
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrInfo.td395 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
425 def top16Zero: PatLeaf<(i32 GPR:$src), [{
787 let MIOperandInfo = (ops GPR, i32imm);
798 let MIOperandInfo = (ops GPR, GPR, i32imm);
809 let MIOperandInfo = (ops GPR, i32imm);
1132 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
1153 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
1209 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
1210 // the GPR i
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td192 let MIOperandInfo = (ops GPR:$base, i32lo16s:$offset, AluOp:$Opcode);
204 let MIOperandInfo = (ops GPR:$Op1, GPR:$Op2, AluOp:$Opcode);
226 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
277 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
281 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
293 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
306 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td108 let MIOperandInfo = (ops GPR, s16imm);
189 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
205 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
312 (outs GPR:$dst),
313 (ins GPR:$src2, GPR:$src),
315 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
317 (outs GPR:$dst),
318 (ins GPR
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H A DBPFMISimplifyPatchable.cpp196 // %1:gpr = LD_imm64 @"llvm.s:0:4$0:2" in processCandidate()
197 // %2:gpr32 = LDW32 %1:gpr, 0 in processCandidate()
198 // %3:gpr = SUBREG_TO_REG 0, %2:gpr32, %subreg.sub_32 in processCandidate()
199 // %4:gpr = ADD_rr %0:gpr, %3:gpr in processCandidate()
236 // .-> %2:gpr = LD_imm64 @"llvm.t:0:0$0:0" in processDstReg()
239 // | %3:gpr = LDD %2:gpr, 0 in processDstReg()
240 // | %4:gpr in processDstReg()
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/freebsd-src/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,apr.yaml7 title: Qualcomm APR/GPR (Asynchronous/Generic Packet Router)
13 This binding describes the Qualcomm APR/GPR, APR/GPR is a IPC protocol for
14 communication between Application processor and QDSP. APR/GPR is mainly
22 - qcom,gpr
54 Selects the processor domain for gpr
97 APR/GPR static port services.
118 - qcom,gpr
186 #include <dt-bindings/soc/qcom,gpr.h>
187 gpr {
188 compatible = "qcom,gpr";
/freebsd-src/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_powerpc.h11 // Computes the offset of the given GPR in the user data area.
12 #define GPR_OFFSET(regname) (offsetof(GPR, regname))
13 #define FPR_OFFSET(regname) (sizeof(GPR) + offsetof(FPR, regname))
14 #define VMX_OFFSET(regname) (sizeof(GPR) + sizeof(FPR) + offsetof(VMX, regname))
15 #define GPR_SIZE(regname) (sizeof(((GPR *)NULL)->regname))
188 #define GPR GPR64 macro
190 #undef GPR
194 #define GPR GPR32 macro
196 #undef GPR
200 #define GPR GPR64 macro
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