Lines Matching full:gpr
395 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
425 def top16Zero: PatLeaf<(i32 GPR:$src), [{
787 let MIOperandInfo = (ops GPR, i32imm);
798 let MIOperandInfo = (ops GPR, GPR, i32imm);
809 let MIOperandInfo = (ops GPR, i32imm);
1132 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
1153 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
1209 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
1210 // the GPR is purely vestigal at this point.
1231 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
1256 let MIOperandInfo = (ops GPR, i32imm);
1274 let MIOperandInfo = (ops GPR:$base, i32imm);
1293 let MIOperandInfo = (ops GPR:$base, i32imm);
1306 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1316 let MIOperandInfo = (ops GPR);
1326 let MIOperandInfo = (ops GPR:$addr, i32imm);
1334 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1410 let MIOperandInfo = (ops GPR:$addr, i32imm);
1421 let MIOperandInfo = (ops GPR:$addr, i32imm);
1485 let MIOperandInfo = (ops GPR, i32imm);
1496 let MIOperandInfo = (ops GPR:$base);
1556 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1558 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1569 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1571 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1584 def rsi : AsI1<opcod, (outs GPR:$Rd),
1585 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1587 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1600 def rsr : AsI1<opcod, (outs GPR:$Rd),
1601 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1603 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1629 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1631 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1642 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1656 def rsi : AsI1<opcod, (outs GPR:$Rd),
1657 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1659 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1672 def rsr : AsI1<opcod, (outs GPR:$Rd),
1673 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1675 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1699 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1701 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1704 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1706 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1710 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1711 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1713 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1717 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1718 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1720 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1731 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1733 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1736 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1737 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1739 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1740 GPR:$Rn))]>,
1743 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1744 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1746 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1747 GPR:$Rn))]>,
1760 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1762 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1774 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1776 [(opnode GPR:$Rn, GPR:$Rm)]>,
1792 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1794 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1860 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1862 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1877 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1891 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1893 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1904 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1906 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1919 def rsi : AsI1<opcod, (outs GPR:$Rd),
1920 (ins GPR:$Rn, so_reg_imm:$shift),
1922 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1961 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1963 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1974 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1987 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1989 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
2002 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2004 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
2026 // GPR and a constrained immediate so that we can use this to match
2028 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2030 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
2038 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
2040 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
2056 // GPR and a constrained immediate so that we can use this to match
2088 // GPR and a constrained immediate so that we can use this to match
2091 (ins GPR:$Rt, addrmode_imm12:$addr),
2093 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
2101 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
2103 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
2117 // GPR and a constrained immediate so that we can use this to match
2223 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
2225 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
2397 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2399 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2403 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2405 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2407 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2409 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2411 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2413 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2415 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2417 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2419 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2421 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2424 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2425 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2427 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2428 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2431 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2432 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2443 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2459 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2462 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2496 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2497 [(brind GPR:$dst)]>,
2504 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2540 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, IIC_Br, "blx\t$func", []>,
2547 4, IIC_Br, [], (BLX GPR:$func)>,
2551 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2560 (BLX_pred GPR:$func, (ops 14, zero_reg))>,
2588 def : ARMPat<(ARMcall GPR:$func), (BLX $func)>,
2592 def : ARMPat<(ARMcall_pred GPR:$func), (BLX_pred $func)>,
2623 (ins GPR:$target, i32imm:$jt),
2625 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2638 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2640 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2659 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2689 (BX GPR:$dst)>, Sched<[WriteBr]>,
2765 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2846 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2858 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2860 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2863 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2865 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2867 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2869 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2873 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2886 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2888 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2890 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2896 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2907 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2919 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2937 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2964 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2976 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2997 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
3010 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
3029 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
3049 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
3065 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
3085 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
3102 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
3126 (ins addr_offset_none:$addr, pred:$p), (outs GPR:$Rt)>;
3136 (outs GPR:$Rt)>;
3140 (outs GPR:$Rt)>;
3146 (outs GPR:$Rt)>;
3151 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
3153 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
3157 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
3175 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
3176 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
3188 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
3189 (ins GPR:$Rt, ldst_so_reg:$addr),
3201 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
3202 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3219 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
3220 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3244 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
3246 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
3248 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
3250 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
3252 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
3254 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
3256 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
3258 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
3268 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3269 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
3271 [(set GPR:$Rn_wb,
3272 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
3273 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3274 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
3276 [(set GPR:$Rn_wb,
3277 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
3278 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3279 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
3281 [(set GPR:$Rn_wb,
3282 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
3283 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3284 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
3286 [(set GPR:$Rn_wb,
3287 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
3288 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3289 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
3291 [(set GPR:$Rn_wb,
3292 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
3297 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
3298 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
3311 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
3312 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
3316 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
3330 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
3331 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
3344 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
3345 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
3363 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
3364 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3383 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
3384 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3401 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3404 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3405 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3424 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3425 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3443 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3446 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3447 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3456 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3457 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3471 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3473 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3475 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3487 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3496 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3507 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3516 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3527 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3536 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3547 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3556 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3585 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3588 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3606 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3648 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3650 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3663 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3664 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3675 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3678 [(set GPR:$Rd, imm0_65535:$imm)]>,
3691 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>,
3696 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3702 (ins GPR:$src, imm0_65535_expr:$imm),
3706 (or (and GPR:$src, 0xffff),
3721 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3722 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3727 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3731 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3732 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3739 def MOVsrl_glue : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3740 [(set GPR:$dst, (ARMsrl_glue GPR:$src))]>, UnaryDP,
3742 def MOVsra_glue : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3743 [(set GPR:$dst, (ARMsra_glue GPR:$src))]>, UnaryDP,
3770 def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src),
3771 (SXTB16 GPR:$Src, 0)>;
3772 def : ARMV6Pat<(int_arm_sxtb16 (rotr GPR:$Src, rot_imm:$rot)),
3773 (SXTB16 GPR:$Src, rot_imm:$rot)>;
3776 def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS),
3777 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>;
3778 def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)),
3779 (SXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>;
3795 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3796 // (UXTB16r_rot GPR:$Src, 3)>;
3797 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3798 (UXTB16 GPR:$Src, 1)>;
3799 def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src),
3800 (UXTB16 GPR:$Src, 0)>;
3801 def : ARMV6Pat<(int_arm_uxtb16 (rotr GPR:$Src, rot_imm:$rot)),
3802 (UXTB16 GPR:$Src, rot_imm:$rot)>;
3817 def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS),
3818 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>;
3819 def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)),
3820 (UXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>;
3900 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3901 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3902 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3903 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3905 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3906 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3908 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3909 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3915 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3916 (SBCri GPR:$src, mod_imm_not:$imm)>;
3917 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3918 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3928 // GPR:$dst = GPR:$a op GPR:$b
3980 def : ARMV5TEPat<(saddsat GPR:$a, GPR:$b),
3981 (QADD GPR:$a, GPR:$b)>;
3982 def : ARMV5TEPat<(ssubsat GPR:$a, GPR:$b),
3983 (QSUB GPR:$a, GPR:$b)>;
4049 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4052 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>,
4064 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4067 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4192 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
4195 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
4207 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
4210 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
4224 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
4226 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
4237 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
4239 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
4270 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
4272 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
4282 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
4283 (BICri GPR:$src, mod_imm_not:$imm)>;
4366 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4368 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
4384 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
4385 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4387 [(set GPR:$RdLo, GPR:$RdHi,
4388 (smullohi GPR:$Rn, GPR:$Rm))]>,
4392 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
4393 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4395 [(set GPR:$RdLo, GPR:$RdHi,
4396 (umullohi GPR:$Rn, GPR:$Rm))]>,
4401 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4402 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4404 [(set GPR:$RdLo, GPR:$RdHi,
4405 (smullohi GPR:$Rn, GPR:$Rm))],
4406 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4410 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4411 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4413 [(set GPR:$RdLo, GPR:$RdHi,
4414 (umullohi GPR:$Rn, GPR:$Rm))],
4415 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4422 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
4423 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4427 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
4428 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4433 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
4434 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4451 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4452 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4454 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4458 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4459 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4461 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4470 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4472 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
4478 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4480 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>,
4486 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
4487 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4489 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
4493 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
4494 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4496 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4500 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
4501 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4506 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
4507 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4509 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4514 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4516 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>,
4520 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4522 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>,
4526 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4528 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>,
4532 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4534 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>,
4538 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4540 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>,
4544 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4546 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>,
4555 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4557 [(set GPRnopc:$Rd, (add GPR:$Ra,
4563 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4565 [(set GPRnopc:$Rd, (add GPR:$Ra,
4571 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4573 [(set GPRnopc:$Rd, (add GPR:$Ra,
4579 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4581 [(set GPRnopc:$Rd, (add GPR:$Ra,
4587 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4590 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4595 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4598 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4622 def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4624 def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4626 def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4628 def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4675 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4680 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4702 def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4704 def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4706 def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4708 def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4744 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4746 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4750 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4752 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4760 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4762 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4765 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4767 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
4771 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4773 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4777 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4779 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4785 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4786 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4788 (REV16 GPR:$Rn)>;
4791 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4793 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4797 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4798 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4799 (REVSH GPR:$Rm)>;
4912 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4913 (CMPri GPR:$src, mod_imm:$imm)>;
4914 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4915 (CMPrr GPR:$src, GPR:$rhs)>;
4916 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4917 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4918 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4919 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4930 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4932 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4946 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4949 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4964 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4967 GPR:$Rn, so_reg_imm:$shift)]>,
5005 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
5006 (CMNri GPR:$src, mod_imm_neg:$imm)>;
5008 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
5009 (CMNri GPR:$src, mod_imm_neg:$imm)>;
5024 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
5026 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
5030 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
5031 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
5040 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
5041 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
5043 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
5047 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
5048 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
5050 [(set GPR:$Rd,
5051 (ARMcmov GPR:$false, so_reg_imm:$shift,
5054 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
5055 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
5057 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
5064 : ARMPseudoInst<(outs GPR:$Rd),
5065 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
5067 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
5073 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
5074 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
5076 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
5083 : ARMPseudoInst<(outs GPR:$Rd),
5084 (ins GPR:$false, i32imm:$src, cmovpred:$p),
5086 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
5091 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
5092 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
5094 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
5181 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
5186 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
5188 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
5197 (outs GPR:$newdst, GPR:$newsrc),
5198 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops),
5200 [(set GPR:$newdst, GPR:$newsrc,
5201 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>;
5259 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5261 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
5262 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5264 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
5265 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5267 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
5274 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5276 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
5277 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5279 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
5280 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5282 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
5291 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5293 [(set GPR:$Rd, (strex_1 GPR:$Rt,
5295 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5297 [(set GPR:$Rd, (strex_2 GPR:$Rt,
5299 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5301 [(set GPR:$Rd, (strex_4 GPR:$Rt,
5304 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
5309 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5311 [(set GPR:$Rd,
5312 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
5313 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5315 [(set GPR:$Rd,
5316 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
5317 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5319 [(set GPR:$Rd,
5320 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
5322 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
5335 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
5336 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
5337 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
5338 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
5340 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
5341 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
5342 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
5343 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
5369 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
5370 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
5371 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
5642 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5644 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn,
5648 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5689 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5691 [(int_arm_mcr2 timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn,
5695 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5834 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5945 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5947 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5955 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5957 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5965 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5967 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5989 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5990 4, IIC_Br, [(brind GPR:$dst)],
5991 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5995 def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst),
5997 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
6007 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
6008 [(set GPR:$dst, (arm_i32imm:$src))]>,
6011 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
6012 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
6020 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
6022 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
6025 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
6027 [(set GPR:$dst,
6032 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
6034 [(set GPR:$dst,
6039 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
6041 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
6113 (SMULBB GPR:$a, GPR:$b)>;
6114 def : ARMV5TEPat<(mul sext_16_node:$a, (sext_bottom_16 GPR:$b)),
6115 (SMULBB GPR:$a, GPR:$b)>;
6116 def : ARMV5TEPat<(mul sext_16_node:$a, (sext_top_16 GPR:$b)),
6117 (SMULBT GPR:$a, GPR:$b)>;
6118 def : ARMV5TEPat<(mul (sext_top_16 GPR:$a), sext_16_node:$b),
6119 (SMULTB GPR:$a, GPR:$b)>;
6120 def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b)),
6121 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
6122 def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_bottom_16 GPR:$b))),
6123 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
6124 def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_top_16 GPR:$b))),
6125 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
6126 def : ARMV5MOPat<(add GPR:$acc, (mul (sext_top_16 GPR:$a), sext_16_node:$b)),
6127 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
6129 def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b),
6130 (SMULBB GPR:$a, GPR:$b)>;
6131 def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b),
6132 (SMULBT GPR:$a, GPR:$b)>;
6133 def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b),
6134 (SMULTB GPR:$a, GPR:$b)>;
6135 def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b),
6136 (SMULTT GPR:$a, GPR:$b)>;
6137 def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b),
6138 (SMULWB GPR:$a, GPR:$b)>;
6139 def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b),
6140 (SMULWT GPR:$a, GPR:$b)>;
6142 def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc),
6143 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
6144 def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc),
6145 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
6146 def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc),
6147 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
6148 def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc),
6149 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>;
6150 def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc),
6151 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
6152 def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc),
6153 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>;
6156 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
6161 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
6162 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
6163 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
6164 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
6165 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
6166 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
6167 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
6170 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
6171 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
6173 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
6174 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
6175 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
6176 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
6189 def : ARMPat<(atomic_store_8 GPR:$val, ldst_so_reg:$ptr),
6190 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
6191 def : ARMPat<(atomic_store_8 GPR:$val, addrmode_imm12:$ptr),
6192 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
6193 def : ARMPat<(atomic_store_16 GPR:$val, addrmode3:$ptr),
6194 (STRH GPR:$val, addrmode3:$ptr)>;
6195 def : ARMPat<(atomic_store_32 GPR:$val, ldst_so_reg:$ptr),
6196 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
6197 def : ARMPat<(atomic_store_32 GPR:$val, addrmode_imm12:$ptr),
6198 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
6283 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6285 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6287 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6296 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6298 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6300 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6354 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6357 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
6360 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6363 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
6368 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6370 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6373 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6375 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6379 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6381 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6383 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6385 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6400 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
6403 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
6406 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
6409 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
6413 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
6431 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
6448 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6451 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6454 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6457 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6465 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
6467 [(set GPR:$Rd, (int_arm_space timm:$size, GPR:$Rn))]>;
6498 def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6499 (ins GPR:$addr, GPR:$desired, GPR:$new),
6502 def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6503 (ins GPR:$addr, GPR:$desired, GPR:$new),
6506 def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6507 (ins GPR:$addr, GPR:$desired, GPR:$new),
6510 def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp),
6511 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new),
6547 def PseudoARMInitUndefGPR : PseudoInst<(outs GPR:$rd), (ins), NoItinerary, []>;