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/freebsd-src/sys/contrib/device-tree/Bindings/remoteproc/
H A Dst,stm32-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/st,stm32-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Fabien Dessenne <fabien.dessenne@foss.st.com>
15 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
19 const: st,stm32mp1-m4
31 reset-names:
33 - const: mcu_rst
34 - const: hold_boot
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H A Dimx-rproc.txt1 NXP iMX6SX/iMX7D Co-Processor Bindings
2 ----------------------------------------
4 This binding provides support for ARM Cortex M4 Co-processor found on some
8 - compatible Should be one of:
9 "fsl,imx7d-cm4"
10 "fsl,imx6sx-cm4"
11 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
12 - syscon Phandle to syscon block which provide access to
16 - memory-region list of phandels to the reserved memory regions.
17 (See: ../reserved-memory/reserved-memory.txt)
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H A Dmtk,scp.txt2 ----------------------------------------
4 This binding provides support for ARM Cortex M4 Co-processor found on some
8 - compatible Should be "mediatek,mt8183-scp"
9 - reg Should contain the address ranges for memory regions:
11 - reg-names Contains the corresponding names for the memory regions:
13 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
14 - clock-names Contains the corresponding name for the clock. This
18 --------
22 for the rpmsg devices - but must contain the following property:
24 - mtk,rpmsg-name Contains the name for the rpmsg device. Used to match
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H A Dfsl,imx-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/fsl,imx-rproc.yaml#
5 $schema: http://devicetree.org/meta-schema
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H A Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
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H A Dmtk,scp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tingha
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/freebsd-src/share/examples/etc/
H A Dmake.conf25 # generated code. This controls processor-specific optimizations in
33 # bdver1, btver2, btver1, amdfam10, opteron-sse3,
34 # athlon64-sse3, k8-sse3, opteron, athlon64, athlon-fx,
35 # k8, athlon-mp, athlon-xp, athlon-4, athlon-tbird,
36 # athlon, k7, geode, k6-3, k6-2, k6
38 # cascadelake, tremont, goldmont-plus, icelake-server,
39 # icelake-client, cannonlake, knm, skylake-avx512, knl,
43 # pentium3m, pentium3, pentium-m, pentium2, pentiumpro,
44 # pentium-mmx, pentium, i486
45 # (VIA CPUs) c7, c3-2, c3
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/freebsd-src/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610m4-colibri.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Device tree for Colibri VF61 Cortex-M4 support
8 /dts-v1/;
12 model = "VF610 Cortex-M4";
17 stdout-path = "serial2:115200";
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_uart2>;
53 vf610-colibri {
H A Dvf610m4-cosmic.dts2 * Device tree for Cosmic+ VF6xx Cortex-M4 support
8 * This file is dual-licensed: you can use it either under the terms
47 /dts-v1/;
51 model = "VF610 Cortex-M4";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_uart3>;
82 vf610-cosmic {
H A Dvf610m4.dtsi2 * Device tree for VF6xx Cortex-M4 support
6 * This file is dual-licensed: you can use it either under the terms
45 #include "../../armv7-m.dtsi"
49 #address-cells = <1>;
50 #size-cells = <1>;
56 interrupt-parent = <&nvic>;
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM4.td1 //==- ARMScheduleM4.td - Cortex-M4 Scheduling Definitions -*- tablegen -*-====//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the SchedRead/Write data for the ARM Cortex-M4 processor.
11 //===----------------------------------------------------------------------===//
14 let IssueWidth = 1; // Only IT can be dual-issued, so assume single-issue
15 let MicroOpBufferSize = 0; // In-order
16 let LoadLatency = 2; // Latency when not pipelined, not pc-relative
28 // Cortex-M4 is in-order.
105 // Most FP instructions are single-cycle latency, except MAC's, Div's and Sqrt's.
H A DARM.td1 //===-- ARM.td - Describe the ARM Target Machine -------
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H A DARMScheduleM55.td1 //==- ARMScheduleM55.td - Arm Cortex-M55 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the scheduling model for the Arm Cortex-M55 processors.
11 //===----------------------------------------------------------------------===//
13 // ===---------------------------------------------------------------------===//
14 // Cortex-M55 is a lot like the M4/M33 in terms of scheduling. It technically
17 // Cortex-M4 are MVE instructions and the ability to dual issue thumb1
24 // pipelines across 4 stages (E1-E4). These pipelines are "control",
33 // the execution of the first-beat-of-the-second-instruction can overlap with
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/freebsd-src/sys/contrib/device-tree/Bindings/arm/stm32/
H A Dst,mlahb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 ML-AH
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/freebsd-src/contrib/opencsd/decoder/source/
H A Dtrc_core_arch_map.cpp44 { "Cortex-A77", { ARCH_V8r3, profile_CortexA } },
45 { "Cortex-A76", { ARCH_V8r3, profile_CortexA } },
46 { "Cortex-A75", { ARCH_V8r3, profile_CortexA } },
47 { "Cortex-A73", { ARCH_V8, profile_CortexA } },
48 { "Cortex-A72", { ARCH_V8, profile_CortexA } },
49 { "Cortex-A65", { ARCH_V8r3, profile_CortexA } },
50 { "Cortex-A57", { ARCH_V8, profile_CortexA } },
51 { "Cortex-A55", { ARCH_V8r3, profile_CortexA } },
52 { "Cortex-A53", { ARCH_V8, profile_CortexA } },
53 { "Cortex-A35", { ARCH_V8, profile_CortexA } },
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/freebsd-src/sys/contrib/device-tree/Bindings/arm/freescale/
H A Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
24 compatible = "fsl,vf610-mscm-ir";
27 interrupt-controller;
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines --------
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/freebsd-src/sys/contrib/device-tree/src/arm/nxp/lpc/
H A Dlpc4350.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
25 compatible = "mmio-sram";
30 compatible = "mmio-sram";
35 compatible = "mmio-sram";
H A Dlpc4357.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
25 compatible = "mmio-sram";
30 compatible = "mmio-sram";
35 compatible = "mmio-sram";
/freebsd-src/sys/contrib/device-tree/Bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bi
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/freebsd-src/contrib/llvm-project/lldb/source/Utility/
H A DArchSpec.cpp1 //===-- ArchSpec.cpp --------
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64.td1 //=- AArch64.td - Describe the AArch64 Target Machine --------*
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/freebsd-src/contrib/bearssl/src/
H A Dconfig.h29 * This file contains compile-time flags that can override the
32 * non-zero integer (normally 1). If the macro is not defined, then
37 * When BR_64 is enabled, 64-bit integer types are assumed to be
38 * efficient (i.e. the architecture has 64-bit registers and can
39 * do 64-bit operations as fast as 32-bit operations).
45 * When BR_LOMUL is enabled, then multiplications of 32-bit values whose
47 * substantially more efficient than 32-bit multiplications that yield
48 * 64-bit results. This is typically the case on low-end ARM Cortex M
49 * systems (M0, M0+, M1, and arguably M3 and M4 as well).
64 * When BR_SLOW_MUL15 is enabled, short multplications (on 15-bit words)
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/freebsd-src/sys/contrib/device-tree/Bindings/firmware/
H A Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
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/freebsd-src/contrib/llvm-project/llvm/lib/TargetParser/
H A DHost.cpp1 //===-- Host.cpp - Implement OS Host Detection -------
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