1*f126890aSEmmanuel Vadot/* 2*f126890aSEmmanuel Vadot * NXP LPC4350 and LPC4330 SoC 3*f126890aSEmmanuel Vadot * 4*f126890aSEmmanuel Vadot * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com> 5*f126890aSEmmanuel Vadot * 6*f126890aSEmmanuel Vadot * This code is released using a dual license strategy: BSD/GPL 7*f126890aSEmmanuel Vadot * You can choose the licence that better fits your requirements. 8*f126890aSEmmanuel Vadot * 9*f126890aSEmmanuel Vadot * Released under the terms of 3-clause BSD License 10*f126890aSEmmanuel Vadot * Released under the terms of GNU General Public License Version 2.0 11*f126890aSEmmanuel Vadot * 12*f126890aSEmmanuel Vadot */ 13*f126890aSEmmanuel Vadot 14*f126890aSEmmanuel Vadot/ { 15*f126890aSEmmanuel Vadot compatible = "nxp,lpc4350", "nxp,lpc4330"; 16*f126890aSEmmanuel Vadot 17*f126890aSEmmanuel Vadot cpus { 18*f126890aSEmmanuel Vadot cpu@0 { 19*f126890aSEmmanuel Vadot compatible = "arm,cortex-m4"; 20*f126890aSEmmanuel Vadot }; 21*f126890aSEmmanuel Vadot }; 22*f126890aSEmmanuel Vadot 23*f126890aSEmmanuel Vadot soc { 24*f126890aSEmmanuel Vadot sram0: sram@10000000 { 25*f126890aSEmmanuel Vadot compatible = "mmio-sram"; 26*f126890aSEmmanuel Vadot reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ 27*f126890aSEmmanuel Vadot }; 28*f126890aSEmmanuel Vadot 29*f126890aSEmmanuel Vadot sram1: sram@10080000 { 30*f126890aSEmmanuel Vadot compatible = "mmio-sram"; 31*f126890aSEmmanuel Vadot reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ 32*f126890aSEmmanuel Vadot }; 33*f126890aSEmmanuel Vadot 34*f126890aSEmmanuel Vadot sram2: sram@20000000 { 35*f126890aSEmmanuel Vadot compatible = "mmio-sram"; 36*f126890aSEmmanuel Vadot reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ 37*f126890aSEmmanuel Vadot }; 38*f126890aSEmmanuel Vadot }; 39*f126890aSEmmanuel Vadot}; 40