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/freebsd-src/sys/contrib/device-tree/Bindings/media/xilinx/
H A Dxlnx,csi2rxss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@amd.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
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/freebsd-src/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_sifive_vector.td1 //==--- riscv_sifive_vector.td - RISC-V SiFive VCIX function list -----
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/freebsd-src/sys/contrib/device-tree/Bindings/soc/imx/
H A Dfsl,imx8mm-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
20 - const: fsl,imx8mm-disp-blk-ctrl
21 - const: syscon
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H A Dfsl,imx8mn-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MN DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
20 - const: fsl,imx8mn-disp-blk-ctrl
21 - const: syscon
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/freebsd-src/sys/contrib/device-tree/Bindings/misc/
H A Difm-csi.txt4 - compatible: "ifm,o2d-csi"
5 - reg: specifies sensor chip select number and associated address range
6 - interrupts: external interrupt line number and interrupt sense mode
8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable"
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
22 csi@3,0 {
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/freebsd-src/sys/contrib/device-tree/Bindings/media/
H A Dnxp,imx7-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx7-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX7 and i.MX8 CSI bridge (CMOS Sensor Interface)
10 - Rui Miguel Silva <rmfrfs@gmail.com>
13 This is device node for the CMOS Sensor Interface (CSI) which enables the
19 - enum:
20 - fsl,imx8mq-csi
21 - fsl,imx7-csi
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H A Dallwinner,sun6i-a31-csi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 CMOS Sensor Interface (CSI)
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun6i-a31-csi
17 - allwinner,sun8i-a83t-csi
18 - allwinner,sun8i-h3-csi
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H A Drenesas,rzg2l-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-csi
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H A Dti,omap3isp.txt4 The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
9 compatible : must contain "ti,omap3-isp"
14 CSI PHYs and receivers registers.
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
19 ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
20 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
21 #clock-cells : Must be 1 --- the ISP provides two external clocks,
24 clock bindings in ../clock/clock-bindings.txt.
27 ---------------------
30 video-interfaces.txt in the same directory.
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H A Dimx.txt5 ---------------------------
12 - compatible : "fsl,imx-capture-subsystem";
13 - ports : Should contain a list of phandles pointing to camera
18 capture-subsystem {
19 compatible = "fsl,imx-capture-subsystem";
25 --------------
27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
29 combined with a D-PHY core mixed into the same register block. In
30 addition this device consists of an i.MX-specific "CSI2IPU gasket"
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H A Dallwinner,sun4i-a10-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 CMOS Sensor Interface (CSI)
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
13 description: |-
20 - const: allwinner,sun4i-a10-csi1
21 - const: allwinner,sun7i-a20-csi0
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/freebsd-src/sys/contrib/device-tree/Bindings/media/i2c/
H A Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
17 - VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
18 - VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.
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H A Dtoshiba,tc358746.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marco Felsch <kernel@pengutronix.de>
12 description: |-
13 The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
14 stream. The direction can be either parallel-in -> csi-out or csi-in ->
15 parallel-out The chip is programmable through I2C and SPI but the SPI
16 interface is only supported in parallel-in -> csi-out mode.
19 parallel-in -> csi-out path.
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H A Dst,st-mipid02.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
15 active at a time. Active port input stream will be de-serialized
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
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/freebsd-src/sys/arm/allwinner/h6/
H A Dh6_padconf.c1 /*-
9 * 2. Redistributions in binary form must reproduce the above copyright
37 { "PC0", 2, 0, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } },
38 { "PC1", 2, 1, { "gpio_in", "gpio_out", "nand", "mmc2" } },
39 { "PC2", 2, 2, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } },
40 { "PC3", 2, 3, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } },
41 { "PC4", 2, 4, { "gpio_in", "gpio_out", "nand", "mmc2" } },
42 { "PC5", 2, 5, { "gpio_in", "gpio_out", "nand", "mmc2", "spi0" } },
43 { "PC6", 2, 6, { "gpio_in", "gpio_out", "nand", "mmc2", "spi0" } },
44 { "PC7", 2, 7, { "gpio_in", "gpio_out", "nand", "mmc2", "spi0" } },
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/freebsd-src/sys/contrib/device-tree/Bindings/phy/
H A Drockchip-inno-csi-dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Heiko Stuebner <heiko@sntech.de>
13 The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
14 connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
19 - rockchip,px30-csi-dphy
20 - rockchip,rk1808-csi-dphy
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/freebsd-src/lib/libkiconv/
H A Dkiconv_sysctl.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
12 * 2. Redistributions in binary form must reproduce the above copyright
43 if (sysctlbyname("kern.iconv.drvlist", NULL, &size, NULL, 0) == -1) in kiconv_lookupconv()
51 if (sysctlbyname("kern.iconv.drvlist", drivers, &size, NULL, 0) == -1) { in kiconv_lookupconv()
69 struct iconv_cspair_info *csi, *csip; in kiconv_lookupcs() local
71 if (sysctlbyname("kern.iconv.cslist", NULL, &size, NULL, 0) == -1) in kiconv_lookupcs()
74 csi = malloc(size); in kiconv_lookupcs()
75 if (csi == NULL) in kiconv_lookupcs()
77 if (sysctlbyname("kern.iconv.cslist", csi, &size, NULL, 0) == -1) { in kiconv_lookupcs()
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/freebsd-src/sys/arm/allwinner/a83t/
H A Da83t_padconf.c1 /*-
9 * 2. Redistributions in binary form must reproduce the above copyright
38 { "PB2", 1, 2, { "gpio_in", "gpio_out", "uart2", "jtag", NULL, NULL, "pb_eint2" }, 6, 2, 0},
48 { "PC0", 2, 0, { "gpio_in", "gpio_out", "nand", "spi0" } },
49 { "PC1", 2, 1, { "gpio_in", "gpio_out", "nand", "spi0" } },
50 { "PC2", 2, 2, { "gpio_in", "gpio_out", "nand", "spi0" } },
51 { "PC3", 2, 3, { "gpio_in", "gpio_out", "nand", "spi0" } },
52 { "PC4", 2, 4, { "gpio_in", "gpio_out", "nand" } },
53 { "PC5", 2, 5, { "gpio_in", "gpio_out", "nand", "mmc2" } },
54 { "PC6", 2, 6, { "gpio_in", "gpio_out", "nand", "mmc2" } },
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/freebsd-src/sys/contrib/device-tree/src/powerpc/
H A Do2d.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
12 gpio-controller;
13 fsl,has-wdt;
14 fsl,wdt-on-boot = <0>;
16 &gpt1 { gpio-controller; };
33 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
34 #address-cells = <1>;
35 #size-cells = <0>;
36 cell-index = <0>;
48 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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/freebsd-src/sys/contrib/device-tree/Bindings/spi/
H A Drenesas,rzv2m-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,rzv2m-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/V2M Clocked Serial Interface (CSI)
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 - $ref: spi-controller.yaml#
18 const: renesas,rzv2m-csi
28 - description: The clock used to generate the output clock (CSICLK)
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/freebsd-src/sys/arm/allwinner/a64/
H A Da64_padconf.c1 /*-
9 * 2. Redistributions in binary form must reproduce the above copyright
40 { "PB2", 1, 2, { "gpio_in", "gpio_out", "uart2", NULL, "jtag", "sim", "pb_eint2" }, 6, 2, 0},
49 { "PC0", 2, 0, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } },
50 { "PC1", 2, 1, { "gpio_in", "gpio_out", "nand", "mmc2", "spi0" } },
51 { "PC2", 2, 2, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } },
52 { "PC3", 2, 3, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } },
53 { "PC4", 2, 4, { "gpio_in", "gpio_out", "nand" } },
54 { "PC5", 2, 5, { "gpio_in", "gpio_out", "nand", "mmc2" } },
55 { "PC6", 2, 6, { "gpio_in", "gpio_out", "nand", "mmc2" } },
[all …]
/freebsd-src/sys/arm/allwinner/h3/
H A Dh3_padconf.c1 /*-
2 * Copyright (c) 2016-2017 Emmanuel Vadot <manu@freebsd.org>
9 * 2. Redistributions in binary form must reproduce the above copyright
43 {"PA2", 0, 2, {"gpio_in", "gpio_out", "uart2", "jtag", NULL, NULL, "pa_eint2", NULL}, 6, 2},
64 {"PC0", 2, 0, {"gpio_in", "gpio_out", "nand", "spi0", NULL, NULL, NULL, NULL}},
65 {"PC1", 2, 1, {"gpio_in", "gpio_out", "nand", "spi0", NULL, NULL, NULL, NULL}},
66 {"PC2", 2, 2, {"gpio_in", "gpio_out", "nand", "spi0", NULL, NULL, NULL, NULL}},
67 {"PC3", 2, 3, {"gpio_in", "gpio_out", "nand", "spi0", NULL, NULL, NULL, NULL}},
68 {"PC4", 2, 4, {"gpio_in", "gpio_out", "nand", NULL, NULL, NULL, NULL, NULL}},
69 {"PC5", 2, 5, {"gpio_in", "gpio_out", "nand", "mmc2", NULL, NULL, NULL, NULL}},
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/bridge/
H A Drenesas,dsi-csi2-tx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car MIPI DSI/CSI-2 Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
14 R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
20 - renesas,r8a779a0-dsi-csi2-tx # for V3U
21 - renesas,r8a779g0-dsi-csi2-tx # for V4H
[all …]
/freebsd-src/sys/arm/allwinner/a33/
H A Da33_padconf.c1 /*-
9 * 2. Redistributions in binary form must reproduce the above copyright
39 {"PB2", 1, 2, {"gpio_in", "gpio_out", "uart2", NULL, "pb_eint2", NULL}, 4, 2, 1},
46 {"PC0", 2, 0, {"gpio_in", "gpio_out", "nand0", "spi0", NULL, NULL, NULL, NULL}},
47 {"PC1", 2, 1, {"gpio_in", "gpio_out", "nand0", "spi0", NULL, NULL, NULL, NULL}},
48 {"PC2", 2, 2, {"gpio_in", "gpio_out", "nand0", "spi0", NULL, NULL, NULL, NULL}},
49 {"PC3", 2, 3, {"gpio_in", "gpio_out", "nand0", "spi0", NULL, NULL, NULL, NULL}},
50 {"PC4", 2, 4, {"gpio_in", "gpio_out", "nand0", NULL, NULL, NULL, NULL, NULL}},
51 {"PC5", 2, 5, {"gpio_in", "gpio_out", "nand0", "mmc2", NULL, NULL, NULL, NULL}},
52 {"PC6", 2, 6, {"gpio_in", "gpio_out", "nand0", "mmc2", NULL, NULL, NULL, NULL}},
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra210-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra CSI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^csi@[0-9a-f]+$"
19 - nvidia,tegra210-csi
26 - description: module clock
[all …]

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