Home
last modified time | relevance | path

Searched full:bit (Results 1 – 25 of 5665) sorted by relevance

12345678910>>...227

/llvm-project/clang/include/clang/Basic/
H A DMSP430Target.def203 // With 16-bit hardware multiplier
204 MSP430_MCU_FEAT("msp430c336", "16bit")
205 MSP430_MCU_FEAT("msp430c337", "16bit")
206 MSP430_MCU_FEAT("msp430cg4616", "16bit")
207 MSP430_MCU_FEAT("msp430cg4617", "16bit")
208 MSP430_MCU_FEAT("msp430cg4618", "16bit")
209 MSP430_MCU_FEAT("msp430cg4619", "16bit")
210 MSP430_MCU_FEAT("msp430e337", "16bit")
211 MSP430_MCU_FEAT("msp430f147", "16bit")
212 MSP430_MCU_FEAT("msp430f148", "16bit")
[all …]
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dwide-scalar-shift-legalization.ll2 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,LE,LE-64BIT
4 ; RUN: llc < %s -mtriple=ppc32-- | FileCheck %s --check-prefixes=ALL,LE,LE-32BIT
50 ; LE-64BIT-LABEL: lshr_8bytes:
51 ; LE-64BIT: # %bb.0:
52 ; LE-64BIT-NEXT: ld 3, 0(3)
53 ; LE-64BIT-NEXT: lwz 4, 0(4)
54 ; LE-64BIT-NEXT: srd 3, 3, 4
55 ; LE-64BIT-NEXT: std 3, 0(5)
56 ; LE-64BIT-NEXT: blr
66 ; LE-32BIT
[all...]
H A Daix-spills-for-eh.ll4 ; RUN: -mtriple=powerpc-unknown-aix < %s | FileCheck %s --check-prefix 32BIT
8 ; RUN: -mtriple=powerpc64-unknown-aix < %s | FileCheck %s --check-prefix 64BIT
14 ; 32BIT-LABEL: _Z5test2iPPKc:
15 ; 32BIT: # %bb.0: # %entry
16 ; 32BIT-NEXT: mflr r0
17 ; 32BIT-NEXT: stwu r1, -464(r1)
18 ; 32BIT-NEXT: stw r0, 472(r1)
19 ; 32BIT-NEXT: stw r30, 320(r1) # 4-byte Folded Spill
20 ; 32BIT-NEXT: li r30, 0
21 ; 32BIT-NEXT: stxv v20, 64(r1) # 16-byte Folded Spill
[all …]
H A Dwide-scalar-shift-by-byte-multiple-legalization.ll2 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,LE,LE-64BIT
4 ; RUN: llc < %s -mtriple=ppc32-- | FileCheck %s --check-prefixes=ALL,LE,LE-32BIT
56 ; LE-64BIT-LABEL: lshr_8bytes:
57 ; LE-64BIT: # %bb.0:
58 ; LE-64BIT-NEXT: lwz 4, 0(4)
59 ; LE-64BIT-NEXT: ld 3, 0(3)
60 ; LE-64BIT-NEXT: slwi 4, 4, 3
61 ; LE-64BIT-NEXT: srd 3, 3, 4
62 ; LE-64BIT-NEXT: std 3, 0(5)
63 ; LE-64BIT
[all...]
H A Daix-vec-arg-spills.ll4 ; RUN: FileCheck %s --check-prefix=32BIT
8 ; RUN: FileCheck %s --check-prefix=64BIT
14 ; 32BIT-LABEL: caller:
15 ; 32BIT: # %bb.0: # %entry
16 ; 32BIT-NEXT: mflr 0
17 ; 32BIT-NEXT: stwu 1, -192(1)
18 ; 32BIT-NEXT: lis 4, 16392
19 ; 32BIT-NEXT: stw 0, 200(1)
20 ; 32BIT-NEXT: li 3, 0
21 ; 32BIT-NEXT: xxlxor 0, 0, 0
[all …]
H A Daix-cc-abi-mir.ll3 ; RUN: FileCheck --check-prefix=32BIT %s
6 ; RUN: FileCheck --check-prefix=64BIT %s
9 ; 32BIT-LABEL: name: call_test_chars
10 ; 32BIT: bb.0.entry:
11 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
12 ; 32BIT-NEXT: $r3 = LI 97
13 ; 32BIT-NEXT: $r4 = LI 97
14 ; 32BIT-NEXT: $r5 = LI 97
15 ; 32BIT-NEXT: $r6 = LI 97
16 ; 32BIT
[all...]
H A Dppc-clear-before-return.ll3 ; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=64BIT
5 ; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=64BIT
7 ; RUN: -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=32BIT %s
9 ; RUN: -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=64BIT %s
13 ; 64BIT-LABEL: test_xor:
14 ; 64BIT: # %bb.0: # %entry
15 ; 64BIT-NEXT: lbz r4, 0(r3)
16 ; 64BIT-NEXT: lbz r3, 1(r3)
17 ; 64BIT-NEXT: xor r3, r3, r4
18 ; 64BIT-NEXT: blr
[all …]
H A Daix-crspill.ll2 ; RUN: --verify-machineinstrs < %s | FileCheck --check-prefix=64BIT %s
5 ; RUN: --verify-machineinstrs < %s | FileCheck --check-prefix=32BIT %s
23 ; 64BIT-LABEL: .killOne:
25 ; 64BIT: mfcr 12
26 ; 64BIT-NEXT: stw 12, 8(1)
27 ; 64BIT-NEXT: mflr 0
28 ; 64BIT-NEXT: stdu 1, -112(1)
29 ; 64BIT: std 0, 128(1)
31 ; 64BIT: # Clobber CR
32 ; 64BIT: bl .do_something
[all …]
H A Daix-vector-stack-caller.ll4 ; RUN: FileCheck %s --check-prefixes=32BIT,LITERAL
8 ; RUN: FileCheck %s --check-prefixes=64BIT,LITERAL
22 ; 32BIT-LABEL: vec_caller:
23 ; 32BIT: # %bb.0: # %entry
24 ; 32BIT-NEXT: mflr 0
25 ; 32BIT-NEXT: stwu 1, -64(1)
26 ; 32BIT-NEXT: lwz 3, L..C0(2) # %const.0
27 ; 32BIT-NEXT: stw 0, 72(1)
28 ; 32BIT-NEXT: xxlxor 34, 34, 34
29 ; 32BIT-NEXT: xxlxor 35, 35, 35
[all …]
H A Dppc64-rop-protection-aix.ll13 ; RUN: -mattr=+rop-protect < %s | FileCheck %s --check-prefix BE-32BIT-P10
16 ; RUN: -mattr=+rop-protect < %s | FileCheck %s --check-prefix BE-32BIT-P9
19 ; RUN: -mattr=+rop-protect < %s | FileCheck %s --check-prefix BE-32BIT-P8
31 ; RUN: -mattr=+rop-protect -mattr=+privileged < %s | FileCheck %s --check-prefix BE-32BIT-P10-PRIV
34 ; RUN: -mattr=+rop-protect -mattr=+privileged < %s | FileCheck %s --check-prefix BE-32BIT-P9-PRIV
37 ; RUN: -mattr=+rop-protect -mattr=+privileged < %s | FileCheck %s --check-prefix BE-32BIT-P8-PRIV
104 ; BE-32BIT-P10-LABEL: caller:
105 ; BE-32BIT-P10: # %bb.0: # %entry
106 ; BE-32BIT-P10-NEXT: mflr r0
107 ; BE-32BIT
[all...]
H A Daix-cc-byval-mem.ll4 ; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
13 ; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
54 ; 32BIT: fixedStack:
55 ; 32BIT-NEXT: - { id: 0, type: default, offset: 56, size: 4, alignment: 8, stack-id: default,
56 ; 32BIT: bb.0.entry:
57 ; 32BIT-NEXT: %[[VAL:[0-9]+]]:gprc = LBZ 0, %fixed-stack.0
58 ; 32BIT-NEXT: $r3 = COPY %[[VAL]]
59 ; 32BIT-NEXT: BLR
61 ; 64BIT: fixedStack:
62 ; 64BIT-NEXT: - { id: 0, type: default, offset: 112, size: 8, alignment: 16, stack-id: default,
[all …]
H A Dppc-32bit-build-vector.ll3 ; RUN: FileCheck %s --check-prefix=32BIT
6 ; RUN: FileCheck %s --check-prefix=64BIT
9 ; 32BIT-LABEL: BuildVectorICE:
10 ; 32BIT: # %bb.0: # %entry
11 ; 32BIT-NEXT: stwu 1, -48(1)
12 ; 32BIT-NEXT: .cfi_def_cfa_offset 48
13 ; 32BIT-NEXT: lxvw4x 34, 0, 3
14 ; 32BIT-NEXT: li 5, 0
15 ; 32BIT-NEXT: addi 3, 1, 16
16 ; 32BIT
[all...]
H A Daix-vector-vararg-caller.ll4 ; RUN: FileCheck --check-prefix=32BIT %s
8 ; RUN: FileCheck --check-prefix=64BIT %s
11 ; 32BIT-LABEL: name: caller
12 ; 32BIT: bb.0.entry:
13 ; 32BIT: ADJCALLSTACKDOWN 176, 0, implicit-def dead $r1, implicit $r1
14 ; 32BIT: [[LWZtoc:%[0-9]+]]:gprc = LWZtoc %const.0, $r2 :: (load (s32) from got)
15 …; 32BIT: [[LXVW4X:%[0-9]+]]:vsrc = LXVW4X $zero, killed [[LWZtoc]] :: (load (s128) from constant…
16 ; 32BIT: [[LI:%[0-9]+]]:gprc = LI 48
17 ; 32BIT: STXVW4X killed [[LXVW4X]], $r1, killed [[LI]] :: (store (s128))
18 ; 32BIT: [[LWZtoc1:%[0-9]+]]:gprc = LWZtoc %const.1, $r2 :: (load (s32) from got)
[all …]
H A Daix-vector-vararg-fixed-caller.ll4 ; RUN: FileCheck --check-prefix=32BIT %s
8 ; RUN: FileCheck --check-prefix=64BIT %s
13 ; 32BIT-LABEL: name: caller
14 ; 32BIT: bb.0.entry:
15 ; 32BIT: ADJCALLSTACKDOWN 88, 0, implicit-def dead $r1, implicit $r1
16 ; 32BIT: [[LWZtoc:%[0-9]+]]:gprc = LWZtoc %const.0, $r2 :: (load (s32) from got)
17 …; 32BIT: [[LXVW4X:%[0-9]+]]:vsrc = LXVW4X $zero, killed [[LWZtoc]] :: (load (s128) from constant…
18 ; 32BIT: [[LI:%[0-9]+]]:gprc = LI 64
19 ; 32BIT: STXVW4X killed [[LXVW4X]], $r1, killed [[LI]] :: (store (s128))
20 ; 32BIT: [[LIS:%[0-9]+]]:gprc = LIS 38314
[all …]
H A Daix64-cc-abi-vaarg.ll2 ; RUN: FileCheck --check-prefix=64BIT %s
34 ; 64BIT-LABEL: name: int_va_arg
35 ; 64BIT-LABEL: liveins:
36 ; 64BIT-DAG: - { reg: '$x3', virtual-reg: '' }
37 ; 64BIT-DAG: - { reg: '$x4', virtual-reg: '' }
38 ; 64BIT-DAG: - { reg: '$x5', virtual-reg: '' }
39 ; 64BIT-DAG: - { reg: '$x6', virtual-reg: '' }
40 ; 64BIT-DAG: - { reg: '$x7', virtual-reg: '' }
41 ; 64BIT-DAG: - { reg: '$x8', virtual-reg: '' }
42 ; 64BIT
[all...]
H A Daix32-cc-abi-vaarg.ll3 ; RUN: llc -O2 -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -stop-after=machine-cp -verify-machineinstrs < %s | FileCheck --check-prefix=32BIT %s
52 ; 32BIT-LABEL: name: int_va_arg
53 ; 32BIT-LABEL: liveins:
54 ; 32BIT-DAG: - { reg: '$r3', virtual-reg: '' }
55 ; 32BIT-DAG: - { reg: '$r4', virtual-reg: '' }
56 ; 32BIT-DAG: - { reg: '$r5', virtual-reg: '' }
57 ; 32BIT-DAG: - { reg: '$r6', virtual-reg: '' }
58 ; 32BIT-DAG: - { reg: '$r7', virtual-reg: '' }
59 ; 32BIT-DAG: - { reg: '$r8', virtual-reg: '' }
60 ; 32BIT
[all...]
H A Daix-cc-byval.ll3 ; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
11 ; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
32 ; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
33 ; 32BIT-NEXT: renamable $r[[REG:[0-9]+]] = LWZtoc @gS1, $r2 :: (load (s32) from got)
34 ; 32BIT-NEXT: renamable $r3 = LBZ 0, killed renamable $r[[REG]] :: (load (s8))
35 ; 32BIT-NEXT: renamable $r3 = RLWINM killed renamable $r3, 24, 0, 7
36 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_1Byte>, csr_aix32, implicit-def dead $lr, implicit $rm,…
37 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
50 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
51 ; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @gS1, $x2 :: (load (s64) from got)
[all …]
/llvm-project/clang/lib/Headers/
H A Dmmintrin.h77 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
78 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
85 /// A 32-bit integer value.
86 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
94 /// Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
102 /// A 64-bit integer vector.
103 /// \returns A 32-bit signed integer value containing the lower 32 bits of the in _mm_cvtm64_si64()
111 /// Casts a 64-bit signed integer value into a 64-bit intege
[all...]
H A Davx2intrin.h36 /// four unsigned 8-bit integers from the 256-bit integer vectors \a X and
40 /// vectors, and another eight using the upper half. These 16-bit values
41 /// are returned in the lower and upper halves of the 256-bit result,
47 /// difference, and sums these four values to form one 16-bit result. The
52 /// bytes from \a Y; the starting bit position for these four bytes is
54 /// sets of four bytes from \a X; the starting bit position for the first
55 /// set of four bytes is specified by \a M[2] times 32. These bit positions
56 /// are all relative to the 128-bit lane for each set of eight operations.
85 /// A 256-bit intege
[all...]
H A Dsmmintrin.h47 /// Rounds up each element of the 128-bit vector of [4 x float] to an
48 /// integer and returns the rounded values in a 128-bit vector of
60 /// A 128-bit vector of [4 x float] values to be rounded up.
61 /// \returns A 128-bit vector of [4 x float] containing the rounded values.
64 /// Rounds up each element of the 128-bit vector of [2 x double] to an
65 /// integer and returns the rounded values in a 128-bit vector of
77 /// A 128-bit vector of [2 x double] values to be rounded up.
78 /// \returns A 128-bit vector of [2 x double] containing the rounded values.
81 /// Copies three upper elements of the first 128-bit vector operand to
82 /// the corresponding three upper elements of the 128-bit resul
[all...]
H A Demmintrin.h83 /// A 128-bit vector of [2 x double] containing one of the source operands.
85 /// A 128-bit vector of [2 x double] containing one of the source operands.
86 /// \returns A 128-bit vector of [2 x double] whose lower 64 bits contain the
95 /// Adds two 128-bit vectors of [2 x double]. in _mm_add_pd()
102 /// A 128-bit vector of [2 x double] containing one of the source operands.
104 /// A 128-bit vector of [2 x double] containing one of the source operands.
105 /// \returns A 128-bit vector of [2 x double] containing the sums of both
123 /// A 128-bit vector of [2 x double] containing the minuend.
125 /// A 128-bit vector of [2 x double] containing the subtrahend.
126 /// \returns A 128-bit vecto
[all...]
/llvm-project/llvm/test/MC/Mips/msa/
H A Dinvalid.s8 addvi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
9 addvi.b $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
10 addvi.h $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
11 addvi.h $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
12 addvi.w $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
13 addvi.w $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
14 addvi.d $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
15 addvi.d $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
16 andi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:22: error: expected 8-bit unsigned immediate
17 andi.b $w1, $w2, 256 # CHECK: :[[@LINE]]:22: error: expected 8-bit unsigned immediate
[all …]
/llvm-project/lldb/test/Shell/BuildScript/
H A Dtoolchain-msvc.test4 RUN: | FileCheck --check-prefix=32BIT %s
7 RUN: | FileCheck --check-prefix=64BIT %s
9 32BIT: Script Arguments:
10 32BIT: Arch: 32
11 32BIT: Compiler: msvc
12 32BIT: Outdir: {{.*}}
13 32BIT: Output: {{.*}}toolchain-msvc.test.tmp\foo.exe
14 32BIT: Nodefaultlib: False
15 32BIT: Opt: none
16 32BIT: Mode: compile
[all …]
/llvm-project/clang/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-xlcompat-macros.c3 // RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefixes=64BIT --check-prefix=…
5 // RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s --check-prefixes=64BIT --check-prefix=…
7 // RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefixes=32BIT --check-prefix=…
9 // RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefixes=64BIT --check-prefix=…
26 // 64BIT-LABEL: @testlabs(
27 // 64BIT-NEXT: entry:
28 // 64BIT-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
29 // 64BIT-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
30 // 64BIT-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
31 // 64BIT-NEXT: [[ABS:%.*]] = call i64 @llvm.abs.i64(i64 [[TMP0]], i1 true)
[all …]
/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchFixupKinds.h26 // 16-bit fixup corresponding to %b16(foo) for instructions like bne.
28 // 21-bit fixup corresponding to %b21(foo) for instructions like bnez.
30 // 26-bit fixup corresponding to %b26(foo)/%plt(foo) for instructions b/bl.
32 // 20-bit fixup corresponding to %abs_hi20(foo) for instruction lu12i.w.
34 // 12-bit fixup corresponding to %abs_lo12(foo) for instruction ori.
36 // 20-bit fixup corresponding to %abs64_lo20(foo) for instruction lu32i.d.
38 // 12-bit fixup corresponding to %abs_hi12(foo) for instruction lu52i.d.
40 // 20-bit fixup corresponding to %le_hi20(foo) for instruction lu12i.w.
42 // 12-bit fixup corresponding to %le_lo12(foo) for instruction ori.
44 // 20-bit fixu
[all...]

12345678910>>...227