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/freebsd-src/sys/contrib/device-tree/Bindings/timer/
H A Drenesas,cmt.yaml14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
30 - renesas,r8a7740-cmt2 # 32-bit CMT2 on R-Mobile A1
31 - renesas,r8a7740-cmt3 # 32-bit CMT3 on R-Mobile A1
32 - renesas,r8a7740-cmt4 # 32
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
13 def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
14 def WriteShiftReg : SchedWrite; // 32 or 64-bit shif
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/freebsd-src/contrib/llvm-project/clang/lib/Headers/
H A Dmmintrin.h42 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
43 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
50 /// A 32-bit integer value.
51 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
52 /// parameter. The upper 32 bit
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H A Dxmmintrin.h42 /// Adds the 32-bit float values in the low-order bits of the operands.
49 /// A 128-bit vector of [4 x float] containing one of the source operands.
50 /// The lower 32 bits of this operand are used in the calculation.
52 /// A 128-bit vector of [4 x float] containing one of the source operands.
53 /// The lower 32 bits of this operand are used in the calculation.
54 /// \returns A 128-bit vector of [4 x float] whose lower 32 bits contain the sum
55 /// of the lower 32 bits of both operands. The upper 96 bits are copied from
64 /// Adds two 128-bit vector
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H A Dia32intrin.h29 /// Finds the first set bit starting from the least significant bit. The result
38 /// A 32-bit integer operand.
39 /// \returns A 32-bit integer containing the bit number.
46 /// Finds the first set bit starting from the most significant bit. The result
55 /// A 32
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H A Dbmi2intrin.h20 /// Copies the unsigned 32-bit integer \a __X and zeroes the upper bits
21 /// starting at bit number \a __Y.
26 /// IF i < 32
36 /// The 32-bit source value to copy.
38 /// The lower 8 bits specify the bit number of the lowest bit to zero.
39 /// \returns The partially zeroed 32-bit value.
46 /// Deposit (scatter) low-order bits from the unsigned 32-bit integer \a __X
47 /// into the 32-bit result, according to the mask in the unsigned 32-bit
66 /// The 32-bit source value to copy.
68 /// The 32-bit mask specifying where to deposit source bits.
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H A Dlwpintrin.h60 /// A 32-bit value is zero-extended and inserted into the 64-bit Data2 field.
62 /// A 32-bit value is inserted into the 32-bit Data1 field.
64 /// A 32-bit immediate value is inserted into the 32-bit Flags field.
82 /// A 32-bit value is zero-extended and inserted into the 64-bit Data2 field.
84 /// A 32-bit value is inserted into the 32-bit Data1 field.
86 /// A 32-bit immediate value is inserted into the 32-bit Flags field.
101 /// A 64-bit value is inserted into the 64-bit Data2 field.
103 /// A 32-bit value is inserted into the 32-bit Data1 field.
105 /// A 32-bit immediate value is inserted into the 32-bit Flags field.
123 /// A 64-bit value is and inserted into the 64-bit Data2 field.
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H A Davxvnniint8intrin.h25 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in \a __A with
26 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate
27 /// signed 16-bit results. Sum these 4 results with the corresponding
28 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
39 /// A 128-bit vector of [16 x char].
41 /// A 128-bit vector of [16 x char].
43 /// A 128-bit vector of [4 x int].
62 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in \a __A with
63 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate
64 /// signed 16-bit results. Sum these 4 results with the corresponding
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H A Davxneconvertintrin.h28 /// Convert scalar BF16 (16-bit) floating-point element
30 /// single-precision (32-bit) floating-point, broadcast it to packed
31 /// single-precision (32-bit) floating-point elements, and store the results in
43 /// A pointer to a 16-bit memory location. The address of the memory
46 /// A 128-bit vector of [4 x float].
51 /// m := j*32
61 /// Convert scalar BF16 (16-bit) floating-point element
63 /// single-precision (32-bit) floating-point, broadcast it to packed
64 /// single-precision (32-bit) floating-point elements, and store the results in
76 /// A pointer to a 16-bit memory location. The address of the memory
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H A Dfmaintrin.h21 /// Computes a multiply-add of 128-bit vectors of [4 x float].
29 /// A 128-bit vector of [4 x float] containing the multiplicand.
31 /// A 128-bit vector of [4 x float] containing the multiplier.
33 /// A 128-bit vector of [4 x float] containing the addend.
34 /// \returns A 128-bit vector of [4 x float] containing the result.
41 /// Computes a multiply-add of 128-bit vectors of [2 x double].
49 /// A 128-bit vector of [2 x double] containing the multiplicand.
51 /// A 128-bit vector of [2 x double] containing the multiplier.
53 /// A 128-bit vector of [2 x double] containing the addend.
54 /// \returns A 128-bit [
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H A Draointintrin.h20 /// Atomically add a 32-bit value at memory operand \a __A and a 32-bit \a __B,
31 /// A pointer to a 32-bit memory location.
33 /// A 32-bit integer value.
42 /// Atomically and a 32-bit value at memory operand \a __A and a 32-bit \a __B,
53 /// A pointer to a 32-bit memory location.
55 /// A 32-bit integer value.
64 /// Atomically or a 32-bit value at memory operand \a __A and a 32-bit \a __B,
75 /// A pointer to a 32-bit memory location.
77 /// A 32-bit integer value.
86 /// Atomically xor a 32-bit value at memory operand \a __A and a 32-bit \a __B,
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H A Davxvnniint16intrin.h26 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
27 /// corresponding unsigned 16-bit integers in \a __B, producing 2 intermediate
28 /// signed 16-bit results. Sum these 2 results with the corresponding
29 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
40 /// A 128-bit vector of [4 x int].
42 /// A 128-bit vector of [8 x short].
44 /// A 128-bit vector of [8 x unsigned short].
46 /// A 128-bit vector of [4 x int].
63 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
64 /// corresponding unsigned 16-bit integers in \a __B, producing 2 intermediate
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H A Davxvnniintrin.h46 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a __A with
47 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate signed
48 /// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
49 /// in \a __S, and store the packed 32-bit results in DST.
69 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a __A with
70 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate signed
71 /// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
72 /// in \a __S using signed saturation, and store the packed 32-bit results in DST.
92 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
93 /// corresponding 16-bit integers in \a __B, producing 2 intermediate signed 32-bit
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H A Df16cintrin.h23 /* NOTE: Intel documents the 128-bit versions of these as being in emmintrin.h,
28 /// Converts a 16-bit half-precision float value into a 32-bit float
36 /// A 16-bit half-precision float value.
37 /// \returns The converted 32-bit float value.
46 /// Converts a 32-bit single-precision float value to a 16-bit
58 /// A 32-bit single-precision float value to be converted to a 16-bit
67 /// \returns The converted 16-bit half-precision float value.
72 /// Converts a 128-bit vector containing 32-bit float values into a
73 /// 128-bit vector containing 16-bit half-precision float values.
84 /// A 128-bit vector containing 32-bit float values.
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/freebsd-src/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsRISCV.def
/freebsd-src/sys/dev/sfxge/common/
H A Defx_regs_pci.h41 * PC_VEND_ID_REG(16bit):
52 * PC_DEV_ID_REG(16bit):
63 * PC_CMD_REG(16bit):
94 * PC_STAT_REG(16bit):
125 * PC_REV_ID_REG(8bit):
136 * PC_CC_REG(24bit):
151 * PC_CACHE_LSIZE_REG(8bit):
162 * PC_MST_LAT_REG(8bit):
173 * PC_HDR_TYPE_REG(8bit):
186 * PC_BIST_REG(8bit):
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H A Defx_regs.h48 * FR_AB_EE_VPD_CFG0_REG_SF(128bit):
54 * FR_AB_EE_VPD_CFG0_REG(128bit):
76 #define FRF_AB_EE_VPD_BASE_LBN 32
94 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):
100 * FR_AB_PCIE_SD_CTL0123_REG(128bit):
130 #define FRF_AB_PCIE_PARLPBK_LBN 32
162 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):
168 * FR_AB_PCIE_SD_CTL45_REG(128bit):
188 #define FRF_AB_PCIE_DTX0_LBN 32
208 * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit):
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/freebsd-src/sys/contrib/device-tree/Bindings/mfd/
H A Dmc13xxx.txt55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
63 vdig : regulator VDIG (register 32, bit 9)
64 vgen : regulator VGEN (register 32, bit 12)
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/freebsd-src/sys/dev/msk/
H A Dif_mskreg.h229 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
230 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
231 #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
232 #define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
233 #define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */
234 #define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */
235 #define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */
236 #define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */
237 #define PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */
238 #define PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */
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/freebsd-src/sys/contrib/openzfs/config/
H A Dhost-cpu-c-abi.m424 dnl contains 32-bit instructions, whereas 'sparc64' code contains 64-bit
25 dnl instructions. A process on a SPARC CPU can be in 32-bit mode or in 64-bit
66 # - 64-bit instruction set, 64-bit pointers, 64-bit 'long': x86_64.
67 # - 64-bit instruction set, 64-bit pointers, 32-bit 'long': x86_64
69 # - 64-bit instruction set, 32-bit pointers, 32-bit 'long': x86_64-x32.
70 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': i386.
103 # - aarch64 instruction set, 64-bit pointers, 64-bit 'long': arm64.
104 # - aarch64 instruction set, 32-bit pointers, 32-bit 'long': arm64-ilp32.
105 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': arm or armhf.
148 # On hppa, the C compiler may be generating 32-bit code or 64-bit
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/freebsd-src/sys/contrib/edk2/Include/Library/
H A DBaseLib.h22 /// The IA-32 architecture context buffer used by SetJump() and LongJump().
165 If String is not aligned on a 16-bit boundary, then ASSERT().
190 If String is not aligned on a 16-bit boundary, then ASSERT().
217 If Destination is not aligned on a 16-bit boundary, then ASSERT().
218 If Source is not aligned on a 16-bit boundary, then ASSERT().
252 If Length > 0 and Destination is not aligned on a 16-bit boundary, then ASSERT().
253 If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().
289 If Destination is not aligned on a 16-bit boundary, then ASSERT().
290 If Source is not aligned on a 16-bit boundary, then ASSERT().
328 If Destination is not aligned on a 16-bit boundary, then ASSERT().
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/freebsd-src/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DInstructionUtils.h15 // Common utilities for manipulating instruction bit fields.
19 // Return the bit field(s) from the most significant bit (msbit) to the
20 // least significant bit (lsbit) of a 64-bit unsigned value.
27 // Return the bit field(s) from the most significant bit (msbit) to the
28 // least significant bit (lsbit) of a 32-bit unsigned value.
31 assert(msbit < 32 && lsbit <= msbit); in Bits32()
35 // Return the bit value from the 'bit' position of a 32-bit unsigned value.
36 static inline uint32_t Bit32(const uint32_t bits, const uint32_t bit) { in Bit32() argument
37 return (bits >> bit) & 1u; in Bit32()
40 static inline uint64_t Bit64(const uint64_t bits, const uint32_t bit) { in Bit64() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64GenRegisterBankInfo.def16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
19 {0, 32, AArch64::FPRRegBank},
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
28 // 6: GPR 32-bit valu
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEFixupKinds.h17 /// fixup_ve_reflong - 32-bit fixup corresponding to foo
20 /// fixup_ve_srel32 - 32-bit fixup corresponding to foo for relative branch
23 /// fixup_ve_hi32 - 32-bit fixup corresponding to foo\@hi
26 /// fixup_ve_lo32 - 32-bit fixup corresponding to foo\@lo
29 /// fixup_ve_pc_hi32 - 32-bit fixup corresponding to foo\@pc_hi
32 /// fixup_ve_pc_lo32 - 32-bit fixup corresponding to foo\@pc_lo
35 /// fixup_ve_got_hi32 - 32-bit fixup corresponding to foo\@got_hi
38 /// fixup_ve_got_lo32 - 32-bit fixup corresponding to foo\@got_lo
41 /// fixup_ve_gotoff_hi32 - 32-bit fixup corresponding to foo\@gotoff_hi
44 /// fixup_ve_gotoff_lo32 - 32-bit fixup corresponding to foo\@gotoff_lo
/freebsd-src/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ELFRelocs/
H A DM68k.def6 ELF_RELOC(R_68K_32, 1) /* Direct 32 bit */
7 ELF_RELOC(R_68K_16, 2) /* Direct 16 bit */
8 ELF_RELOC(R_68K_8, 3) /* Direct 8 bit */
9 ELF_RELOC(R_68K_PC32, 4) /* PC relative 32 bit */
10 ELF_RELOC(R_68K_PC16, 5) /* PC relative 16 bit */
11 ELF_RELOC(R_68K_PC8, 6) /* PC relative 8 bit */
12 ELF_RELOC(R_68K_GOTPCREL32, 7) /* 32 bit PC relative GOT entry */
13 ELF_RELOC(R_68K_GOTPCREL16, 8) /* 16 bit PC relative GOT entry */
14 ELF_RELOC(R_68K_GOTPCREL8, 9) /* 8 bit PC relative GOT entry */
15 ELF_RELOC(R_68K_GOTOFF32, 10) /* 32 bit GOT offset */
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