xref: /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSchedule.td (revision 0fca6ea1d4eea4c934cfff25ac9ee8ad6fe95583)
106c3fb27SDimitry Andric//===-- RISCVSchedule.td - RISC-V Scheduling Definitions ---*- tablegen -*-===//
213138422SDimitry Andric//
313138422SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
413138422SDimitry Andric// See https://llvm.org/LICENSE.txt for license information.
513138422SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
613138422SDimitry Andric//
713138422SDimitry Andric//===----------------------------------------------------------------------===//
813138422SDimitry Andric
913138422SDimitry Andric/// Define scheduler resources associated with def operands.
1013138422SDimitry Andricdef WriteIALU       : SchedWrite;    // 32 or 64-bit integer ALU operations
1113138422SDimitry Andricdef WriteIALU32     : SchedWrite;    // 32-bit integer ALU operations on RV64I
12fe6060f1SDimitry Andricdef WriteShiftImm   : SchedWrite;    // 32 or 64-bit shift by immediate operations
13fe6060f1SDimitry Andricdef WriteShiftImm32 : SchedWrite;    // 32-bit shift by immediate operations on RV64Ix
14fe6060f1SDimitry Andricdef WriteShiftReg   : SchedWrite;    // 32 or 64-bit shift by immediate operations
15fe6060f1SDimitry Andricdef WriteShiftReg32 : SchedWrite;    // 32-bit shift by immediate operations on RV64Ix
16*0fca6ea1SDimitry Andricdef WriteIDiv       : SchedWrite;    // 32-bit or 64-bit divide
17*0fca6ea1SDimitry Andricdef WriteIDiv32     : SchedWrite;    // 32-bit divide on RV64I
18*0fca6ea1SDimitry Andricdef WriteIRem       : SchedWrite;    // 32-bit or 64-bit remainder
19*0fca6ea1SDimitry Andricdef WriteIRem32     : SchedWrite;    // 32-bit remainder on RV64I
2013138422SDimitry Andricdef WriteIMul       : SchedWrite;    // 32-bit or 64-bit multiply
2113138422SDimitry Andricdef WriteIMul32     : SchedWrite;    // 32-bit multiply on RV64I
2213138422SDimitry Andricdef WriteJmp        : SchedWrite;    // Jump
2313138422SDimitry Andricdef WriteJal        : SchedWrite;    // Jump and link
2413138422SDimitry Andricdef WriteJalr       : SchedWrite;    // Jump and link register
2513138422SDimitry Andricdef WriteNop        : SchedWrite;
2613138422SDimitry Andricdef WriteLDB        : SchedWrite;    // Load byte
2713138422SDimitry Andricdef WriteLDH        : SchedWrite;    // Load half-word
2813138422SDimitry Andricdef WriteLDW        : SchedWrite;    // Load word
2913138422SDimitry Andricdef WriteLDD        : SchedWrite;    // Load double-word
3013138422SDimitry Andricdef WriteCSR        : SchedWrite;    // CSR instructions
3113138422SDimitry Andricdef WriteSTB        : SchedWrite;    // Store byte
3213138422SDimitry Andricdef WriteSTH        : SchedWrite;    // Store half-word
3313138422SDimitry Andricdef WriteSTW        : SchedWrite;    // Store word
3413138422SDimitry Andricdef WriteSTD        : SchedWrite;    // Store double-word
35*0fca6ea1SDimitry Andricdef WriteAtomicB    : SchedWrite;    //Atomic memory operation byte size
36*0fca6ea1SDimitry Andricdef WriteAtomicH    : SchedWrite;    //Atomic memory operation halfword size
3713138422SDimitry Andricdef WriteAtomicW    : SchedWrite;    //Atomic memory operation word size
3813138422SDimitry Andricdef WriteAtomicD    : SchedWrite;    //Atomic memory operation double word size
3913138422SDimitry Andricdef WriteAtomicLDW  : SchedWrite;    // Atomic load word
4013138422SDimitry Andricdef WriteAtomicLDD  : SchedWrite;    // Atomic load double word
4113138422SDimitry Andricdef WriteAtomicSTW  : SchedWrite;    // Atomic store word
4213138422SDimitry Andricdef WriteAtomicSTD  : SchedWrite;    // Atomic store double word
43bdd1243dSDimitry Andricdef WriteFAdd16     : SchedWrite;    // 16-bit floating point addition/subtraction
44bdd1243dSDimitry Andricdef WriteFAdd32     : SchedWrite;    // 32-bit floating point addition/subtraction
45bdd1243dSDimitry Andricdef WriteFAdd64     : SchedWrite;    // 64-bit floating point addition/subtraction
46fe6060f1SDimitry Andricdef WriteFMul16     : SchedWrite;    // 16-bit floating point multiply
4713138422SDimitry Andricdef WriteFMul32     : SchedWrite;    // 32-bit floating point multiply
4813138422SDimitry Andricdef WriteFMul64     : SchedWrite;    // 64-bit floating point multiply
49bdd1243dSDimitry Andricdef WriteFMA16      : SchedWrite;    // 16-bit floating point fused multiply-add
50bdd1243dSDimitry Andricdef WriteFMA32      : SchedWrite;    // 32-bit floating point fused multiply-add
51fe6060f1SDimitry Andricdef WriteFMA64      : SchedWrite;    // 64-bit floating point fused multiply-add
52fe6060f1SDimitry Andricdef WriteFDiv16     : SchedWrite;    // 16-bit floating point divide
5313138422SDimitry Andricdef WriteFDiv32     : SchedWrite;    // 32-bit floating point divide
5413138422SDimitry Andricdef WriteFDiv64     : SchedWrite;    // 64-bit floating point divide
55fe6060f1SDimitry Andricdef WriteFSqrt16    : SchedWrite;    // 16-bit floating point sqrt
5613138422SDimitry Andricdef WriteFSqrt32    : SchedWrite;    // 32-bit floating point sqrt
5713138422SDimitry Andricdef WriteFSqrt64    : SchedWrite;    // 64-bit floating point sqrt
5813138422SDimitry Andric
5913138422SDimitry Andric// Integer to float conversions
60fe6060f1SDimitry Andricdef WriteFCvtI32ToF16  : SchedWrite;
6113138422SDimitry Andricdef WriteFCvtI32ToF32  : SchedWrite;
6213138422SDimitry Andricdef WriteFCvtI32ToF64  : SchedWrite;
63fe6060f1SDimitry Andricdef WriteFCvtI64ToF16  : SchedWrite;    // RV64I only
6413138422SDimitry Andricdef WriteFCvtI64ToF32  : SchedWrite;    // RV64I only
6513138422SDimitry Andricdef WriteFCvtI64ToF64  : SchedWrite;    // RV64I only
6613138422SDimitry Andric
6713138422SDimitry Andric//Float to integer conversions
68fe6060f1SDimitry Andricdef WriteFCvtF16ToI32  : SchedWrite;
69fe6060f1SDimitry Andricdef WriteFCvtF16ToI64  : SchedWrite;    // RV64I only
7013138422SDimitry Andricdef WriteFCvtF32ToI32  : SchedWrite;
7113138422SDimitry Andricdef WriteFCvtF32ToI64  : SchedWrite;    // RV64I only
7213138422SDimitry Andricdef WriteFCvtF64ToI32  : SchedWrite;
7313138422SDimitry Andricdef WriteFCvtF64ToI64  : SchedWrite;    // RV64I only
7413138422SDimitry Andric
7513138422SDimitry Andric// Float to float conversions
7613138422SDimitry Andricdef WriteFCvtF32ToF64  : SchedWrite;
7713138422SDimitry Andricdef WriteFCvtF64ToF32  : SchedWrite;
78fe6060f1SDimitry Andricdef WriteFCvtF16ToF32  : SchedWrite;
79fe6060f1SDimitry Andricdef WriteFCvtF32ToF16  : SchedWrite;
80fe6060f1SDimitry Andricdef WriteFCvtF16ToF64  : SchedWrite;
81fe6060f1SDimitry Andricdef WriteFCvtF64ToF16  : SchedWrite;
8213138422SDimitry Andric
8306c3fb27SDimitry Andric// Zfa found instructions.
8406c3fb27SDimitry Andricdef WriteFRoundF32     : SchedWrite;
8506c3fb27SDimitry Andricdef WriteFRoundF64     : SchedWrite;
8606c3fb27SDimitry Andricdef WriteFRoundF16     : SchedWrite;
8706c3fb27SDimitry Andric
88fe6060f1SDimitry Andricdef WriteFClass16   : SchedWrite;    // 16-bit floating point classify
8913138422SDimitry Andricdef WriteFClass32   : SchedWrite;    // 32-bit floating point classify
9013138422SDimitry Andricdef WriteFClass64   : SchedWrite;    // 64-bit floating point classify
91fe6060f1SDimitry Andricdef WriteFCmp16     : SchedWrite;    // 16-bit floating point compare
9213138422SDimitry Andricdef WriteFCmp32     : SchedWrite;    // 32-bit floating point compare
9313138422SDimitry Andricdef WriteFCmp64     : SchedWrite;    // 64-bit floating point compare
94fe6060f1SDimitry Andricdef WriteFSGNJ16    : SchedWrite;    // 16-bit floating point sign-injection
955ffd83dbSDimitry Andricdef WriteFSGNJ32    : SchedWrite;    // 32-bit floating point sign-injection
965ffd83dbSDimitry Andricdef WriteFSGNJ64    : SchedWrite;    // 64-bit floating point sign-injection
97fe6060f1SDimitry Andricdef WriteFMinMax16  : SchedWrite;    // 16-bit floating point min or max
985ffd83dbSDimitry Andricdef WriteFMinMax32  : SchedWrite;    // 32-bit floating point min or max
995ffd83dbSDimitry Andricdef WriteFMinMax64  : SchedWrite;    // 64-bit floating point min or max
10013138422SDimitry Andric
101fe6060f1SDimitry Andricdef WriteFMovF16ToI16     : SchedWrite;
102fe6060f1SDimitry Andricdef WriteFMovI16ToF16     : SchedWrite;
10313138422SDimitry Andricdef WriteFMovF32ToI32     : SchedWrite;
10413138422SDimitry Andricdef WriteFMovI32ToF32     : SchedWrite;
10513138422SDimitry Andricdef WriteFMovF64ToI64     : SchedWrite;    // RV64I only
10613138422SDimitry Andricdef WriteFMovI64ToF64     : SchedWrite;    // RV64I only
10713138422SDimitry Andric
10806c3fb27SDimitry Andricdef WriteFLI16        : SchedWrite;    // Floating point constant load
10906c3fb27SDimitry Andricdef WriteFLI32        : SchedWrite;    // Floating point constant load
11006c3fb27SDimitry Andricdef WriteFLI64        : SchedWrite;    // Floating point constant load
11106c3fb27SDimitry Andric
112fe6060f1SDimitry Andricdef WriteFLD16        : SchedWrite;    // Floating point sp load
11313138422SDimitry Andricdef WriteFLD32        : SchedWrite;    // Floating point sp load
11413138422SDimitry Andricdef WriteFLD64        : SchedWrite;    // Floating point dp load
115fe6060f1SDimitry Andricdef WriteFST16        : SchedWrite;    // Floating point sp store
11613138422SDimitry Andricdef WriteFST32        : SchedWrite;    // Floating point sp store
11713138422SDimitry Andricdef WriteFST64        : SchedWrite;    // Floating point dp store
11813138422SDimitry Andric
119bdd1243dSDimitry Andric// short forward branch for Bullet
120bdd1243dSDimitry Andricdef WriteSFB        : SchedWrite;
12106c3fb27SDimitry Andricdef ReadSFBJmp      : SchedRead;
12206c3fb27SDimitry Andricdef ReadSFBALU      : SchedRead;
123bdd1243dSDimitry Andric
12413138422SDimitry Andric/// Define scheduler resources associated with use operands.
12513138422SDimitry Andricdef ReadJmp         : SchedRead;
12613138422SDimitry Andricdef ReadJalr        : SchedRead;
12713138422SDimitry Andricdef ReadCSR         : SchedRead;
12813138422SDimitry Andricdef ReadMemBase     : SchedRead;
1295ffd83dbSDimitry Andricdef ReadFMemBase    : SchedRead;
13013138422SDimitry Andricdef ReadStoreData   : SchedRead;
131bdd1243dSDimitry Andricdef ReadFStoreData  : SchedRead;
13213138422SDimitry Andricdef ReadIALU        : SchedRead;
13313138422SDimitry Andricdef ReadIALU32      : SchedRead;    // 32-bit integer ALU operations on RV64I
134fe6060f1SDimitry Andricdef ReadShiftImm    : SchedRead;
135fe6060f1SDimitry Andricdef ReadShiftImm32  : SchedRead;    // 32-bit shift by immediate operations on RV64Ix
136fe6060f1SDimitry Andricdef ReadShiftReg    : SchedRead;
137fe6060f1SDimitry Andricdef ReadShiftReg32  : SchedRead;    // 32-bit shift by register operations on RV64Ix
13813138422SDimitry Andricdef ReadIDiv        : SchedRead;
13913138422SDimitry Andricdef ReadIDiv32      : SchedRead;
140*0fca6ea1SDimitry Andricdef ReadIRem        : SchedRead;
141*0fca6ea1SDimitry Andricdef ReadIRem32      : SchedRead;
14213138422SDimitry Andricdef ReadIMul        : SchedRead;
14313138422SDimitry Andricdef ReadIMul32      : SchedRead;
144*0fca6ea1SDimitry Andricdef ReadAtomicBA    : SchedRead;
145*0fca6ea1SDimitry Andricdef ReadAtomicBD    : SchedRead;
146*0fca6ea1SDimitry Andricdef ReadAtomicHA    : SchedRead;
147*0fca6ea1SDimitry Andricdef ReadAtomicHD    : SchedRead;
14813138422SDimitry Andricdef ReadAtomicWA    : SchedRead;
14913138422SDimitry Andricdef ReadAtomicWD    : SchedRead;
15013138422SDimitry Andricdef ReadAtomicDA    : SchedRead;
15113138422SDimitry Andricdef ReadAtomicDD    : SchedRead;
15213138422SDimitry Andricdef ReadAtomicLDW   : SchedRead;    // Atomic load word
15313138422SDimitry Andricdef ReadAtomicLDD   : SchedRead;    // Atomic load double word
15413138422SDimitry Andricdef ReadAtomicSTW   : SchedRead;    // Atomic store word
15513138422SDimitry Andricdef ReadAtomicSTD   : SchedRead;    // Atomic store double word
156bdd1243dSDimitry Andricdef ReadFAdd16      : SchedRead;    // 16-bit floating point addition/subtraction
157bdd1243dSDimitry Andricdef ReadFAdd32      : SchedRead;    // 32-bit floating point addition/subtraction
158bdd1243dSDimitry Andricdef ReadFAdd64      : SchedRead;    // 64-bit floating point addition/subtraction
159fe6060f1SDimitry Andricdef ReadFMul16      : SchedRead;    // 16-bit floating point multiply
16013138422SDimitry Andricdef ReadFMul32      : SchedRead;    // 32-bit floating point multiply
16113138422SDimitry Andricdef ReadFMul64      : SchedRead;    // 64-bit floating point multiply
162bdd1243dSDimitry Andricdef ReadFMA16       : SchedRead;    // 16-bit floating point fused multiply-add
1635f757f3fSDimitry Andricdef ReadFMA16Addend : SchedRead;    // 16-bit floating point fused multiply-add (addend)
164bdd1243dSDimitry Andricdef ReadFMA32       : SchedRead;    // 32-bit floating point fused multiply-add
1655f757f3fSDimitry Andricdef ReadFMA32Addend : SchedRead;    // 32-bit floating point fused multiply-add (addend)
166fe6060f1SDimitry Andricdef ReadFMA64       : SchedRead;    // 64-bit floating point fused multiply-add
1675f757f3fSDimitry Andricdef ReadFMA64Addend : SchedRead;    // 64-bit floating point fused multiply-add (addend)
168fe6060f1SDimitry Andricdef ReadFDiv16      : SchedRead;    // 16-bit floating point divide
16913138422SDimitry Andricdef ReadFDiv32      : SchedRead;    // 32-bit floating point divide
17013138422SDimitry Andricdef ReadFDiv64      : SchedRead;    // 64-bit floating point divide
171fe6060f1SDimitry Andricdef ReadFSqrt16     : SchedRead;    // 16-bit floating point sqrt
17213138422SDimitry Andricdef ReadFSqrt32     : SchedRead;    // 32-bit floating point sqrt
17313138422SDimitry Andricdef ReadFSqrt64     : SchedRead;    // 64-bit floating point sqrt
174fe6060f1SDimitry Andricdef ReadFCmp16      : SchedRead;
17513138422SDimitry Andricdef ReadFCmp32      : SchedRead;
17613138422SDimitry Andricdef ReadFCmp64      : SchedRead;
177fe6060f1SDimitry Andricdef ReadFSGNJ16     : SchedRead;
1785ffd83dbSDimitry Andricdef ReadFSGNJ32     : SchedRead;
1795ffd83dbSDimitry Andricdef ReadFSGNJ64     : SchedRead;
180fe6060f1SDimitry Andricdef ReadFMinMax16   : SchedRead;
1815ffd83dbSDimitry Andricdef ReadFMinMax32   : SchedRead;
1825ffd83dbSDimitry Andricdef ReadFMinMax64   : SchedRead;
183fe6060f1SDimitry Andricdef ReadFCvtF16ToI32     : SchedRead;
184fe6060f1SDimitry Andricdef ReadFCvtF16ToI64     : SchedRead;
18513138422SDimitry Andricdef ReadFCvtF32ToI32     : SchedRead;
18613138422SDimitry Andricdef ReadFCvtF32ToI64     : SchedRead;
18713138422SDimitry Andricdef ReadFCvtF64ToI32     : SchedRead;
18813138422SDimitry Andricdef ReadFCvtF64ToI64     : SchedRead;
189fe6060f1SDimitry Andricdef ReadFCvtI32ToF16     : SchedRead;
19013138422SDimitry Andricdef ReadFCvtI32ToF32     : SchedRead;
19113138422SDimitry Andricdef ReadFCvtI32ToF64     : SchedRead;
192fe6060f1SDimitry Andricdef ReadFCvtI64ToF16     : SchedRead;
19313138422SDimitry Andricdef ReadFCvtI64ToF32     : SchedRead;
19413138422SDimitry Andricdef ReadFCvtI64ToF64     : SchedRead;
195fe6060f1SDimitry Andricdef ReadFMovF16ToI16     : SchedRead;
196fe6060f1SDimitry Andricdef ReadFMovI16ToF16     : SchedRead;
19713138422SDimitry Andricdef ReadFMovF32ToI32     : SchedRead;
19813138422SDimitry Andricdef ReadFMovI32ToF32     : SchedRead;
19913138422SDimitry Andricdef ReadFMovF64ToI64     : SchedRead;
20013138422SDimitry Andricdef ReadFMovI64ToF64     : SchedRead;
20113138422SDimitry Andricdef ReadFCvtF32ToF64     : SchedRead;
20213138422SDimitry Andricdef ReadFCvtF64ToF32     : SchedRead;
203fe6060f1SDimitry Andricdef ReadFCvtF16ToF32     : SchedRead;
204fe6060f1SDimitry Andricdef ReadFCvtF32ToF16     : SchedRead;
205fe6060f1SDimitry Andricdef ReadFCvtF16ToF64     : SchedRead;
206fe6060f1SDimitry Andricdef ReadFCvtF64ToF16     : SchedRead;
20706c3fb27SDimitry Andricdef ReadFRoundF16        : SchedRead;
20806c3fb27SDimitry Andricdef ReadFRoundF32        : SchedRead;
20906c3fb27SDimitry Andricdef ReadFRoundF64        : SchedRead;
210fe6060f1SDimitry Andricdef ReadFClass16         : SchedRead;
21113138422SDimitry Andricdef ReadFClass32         : SchedRead;
21213138422SDimitry Andricdef ReadFClass64         : SchedRead;
213fe6060f1SDimitry Andric
214fe6060f1SDimitry Andricmulticlass UnsupportedSchedZfh {
215fe6060f1SDimitry Andriclet Unsupported = true in {
216bdd1243dSDimitry Andricdef : WriteRes<WriteFAdd16, []>;
217fe6060f1SDimitry Andricdef : WriteRes<WriteFClass16, []>;
218fe6060f1SDimitry Andricdef : WriteRes<WriteFCvtF16ToF64, []>;
219fe6060f1SDimitry Andricdef : WriteRes<WriteFCvtF64ToF16, []>;
220fe6060f1SDimitry Andricdef : WriteRes<WriteFCvtI64ToF16, []>;
221fe6060f1SDimitry Andricdef : WriteRes<WriteFCvtF32ToF16, []>;
222fe6060f1SDimitry Andricdef : WriteRes<WriteFCvtI32ToF16, []>;
223fe6060f1SDimitry Andricdef : WriteRes<WriteFCvtF16ToI64, []>;
224fe6060f1SDimitry Andricdef : WriteRes<WriteFCvtF16ToF32, []>;
225fe6060f1SDimitry Andricdef : WriteRes<WriteFCvtF16ToI32, []>;
226fe6060f1SDimitry Andricdef : WriteRes<WriteFDiv16, []>;
227fe6060f1SDimitry Andricdef : WriteRes<WriteFCmp16, []>;
228fe6060f1SDimitry Andricdef : WriteRes<WriteFLD16, []>;
229fe6060f1SDimitry Andricdef : WriteRes<WriteFMA16, []>;
230fe6060f1SDimitry Andricdef : WriteRes<WriteFMinMax16, []>;
231fe6060f1SDimitry Andricdef : WriteRes<WriteFMul16, []>;
232fe6060f1SDimitry Andricdef : WriteRes<WriteFMovI16ToF16, []>;
233fe6060f1SDimitry Andricdef : WriteRes<WriteFMovF16ToI16, []>;
234fe6060f1SDimitry Andricdef : WriteRes<WriteFSGNJ16, []>;
235fe6060f1SDimitry Andricdef : WriteRes<WriteFST16, []>;
236fe6060f1SDimitry Andricdef : WriteRes<WriteFSqrt16, []>;
237fe6060f1SDimitry Andric
238bdd1243dSDimitry Andricdef : ReadAdvance<ReadFAdd16, 0>;
239fe6060f1SDimitry Andricdef : ReadAdvance<ReadFClass16, 0>;
240fe6060f1SDimitry Andricdef : ReadAdvance<ReadFCvtF16ToF64, 0>;
241fe6060f1SDimitry Andricdef : ReadAdvance<ReadFCvtF64ToF16, 0>;
242fe6060f1SDimitry Andricdef : ReadAdvance<ReadFCvtI64ToF16, 0>;
243fe6060f1SDimitry Andricdef : ReadAdvance<ReadFCvtF32ToF16, 0>;
244fe6060f1SDimitry Andricdef : ReadAdvance<ReadFCvtI32ToF16, 0>;
245fe6060f1SDimitry Andricdef : ReadAdvance<ReadFCvtF16ToI64, 0>;
246fe6060f1SDimitry Andricdef : ReadAdvance<ReadFCvtF16ToF32, 0>;
247fe6060f1SDimitry Andricdef : ReadAdvance<ReadFCvtF16ToI32, 0>;
248fe6060f1SDimitry Andricdef : ReadAdvance<ReadFDiv16, 0>;
249fe6060f1SDimitry Andricdef : ReadAdvance<ReadFCmp16, 0>;
250fe6060f1SDimitry Andricdef : ReadAdvance<ReadFMA16, 0>;
251fe6060f1SDimitry Andricdef : ReadAdvance<ReadFMinMax16, 0>;
252fe6060f1SDimitry Andricdef : ReadAdvance<ReadFMul16, 0>;
253fe6060f1SDimitry Andricdef : ReadAdvance<ReadFMovI16ToF16, 0>;
254fe6060f1SDimitry Andricdef : ReadAdvance<ReadFMovF16ToI16, 0>;
255fe6060f1SDimitry Andricdef : ReadAdvance<ReadFSGNJ16, 0>;
256fe6060f1SDimitry Andricdef : ReadAdvance<ReadFSqrt16, 0>;
257fe6060f1SDimitry Andric} // Unsupported = true
258fe6060f1SDimitry Andric}
259fe6060f1SDimitry Andric
260*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedF {
261*0fca6ea1SDimitry Andriclet Unsupported = true in {
262*0fca6ea1SDimitry Andricdef : WriteRes<WriteFST32, []>;
263*0fca6ea1SDimitry Andricdef : WriteRes<WriteFLD32, []>;
264*0fca6ea1SDimitry Andricdef : WriteRes<WriteFAdd32, []>;
265*0fca6ea1SDimitry Andricdef : WriteRes<WriteFSGNJ32, []>;
266*0fca6ea1SDimitry Andricdef : WriteRes<WriteFMinMax32, []>;
267*0fca6ea1SDimitry Andricdef : WriteRes<WriteFCvtI32ToF32, []>;
268*0fca6ea1SDimitry Andricdef : WriteRes<WriteFCvtI64ToF32, []>;
269*0fca6ea1SDimitry Andricdef : WriteRes<WriteFCvtF32ToI32, []>;
270*0fca6ea1SDimitry Andricdef : WriteRes<WriteFCvtF32ToI64, []>;
271*0fca6ea1SDimitry Andricdef : WriteRes<WriteFClass32, []>;
272*0fca6ea1SDimitry Andricdef : WriteRes<WriteFCmp32, []>;
273*0fca6ea1SDimitry Andricdef : WriteRes<WriteFMovF32ToI32, []>;
274*0fca6ea1SDimitry Andricdef : WriteRes<WriteFMovI32ToF32, []>;
275*0fca6ea1SDimitry Andricdef : WriteRes<WriteFMul32, []>;
276*0fca6ea1SDimitry Andricdef : WriteRes<WriteFMA32, []>;
277*0fca6ea1SDimitry Andricdef : WriteRes<WriteFDiv32, []>;
278*0fca6ea1SDimitry Andricdef : WriteRes<WriteFSqrt32, []>;
279*0fca6ea1SDimitry Andric
280*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFAdd32, 0>;
281*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFMul32, 0>;
282*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFMA32, 0>;
283*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFMA32Addend, 0>;
284*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFDiv32, 0>;
285*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFSqrt32, 0>;
286*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFCmp32, 0>;
287*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFSGNJ32, 0>;
288*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFMinMax32, 0>;
289*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFCvtF32ToI32, 0>;
290*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFCvtF32ToI64, 0>;
291*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFCvtI32ToF32, 0>;
292*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFCvtI64ToF32, 0>;
293*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFMovF32ToI32, 0>;
294*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFMovI32ToF32, 0>;
295*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFClass32, 0>;
296*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFStoreData, 0>;
297*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFMemBase, 0>;
298*0fca6ea1SDimitry Andric} // Unsupported = true
299*0fca6ea1SDimitry Andric}
300*0fca6ea1SDimitry Andric
301*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedD {
302*0fca6ea1SDimitry Andriclet Unsupported = true in {
303*0fca6ea1SDimitry Andricdef : WriteRes<WriteFST64, []>;
304*0fca6ea1SDimitry Andricdef : WriteRes<WriteFLD64, []>;
305*0fca6ea1SDimitry Andricdef : WriteRes<WriteFAdd64, []>;
306*0fca6ea1SDimitry Andricdef : WriteRes<WriteFSGNJ64, []>;
307*0fca6ea1SDimitry Andricdef : WriteRes<WriteFMinMax64, []>;
308*0fca6ea1SDimitry Andricdef : WriteRes<WriteFCvtI32ToF64, []>;
309*0fca6ea1SDimitry Andricdef : WriteRes<WriteFCvtI64ToF64, []>;
310*0fca6ea1SDimitry Andricdef : WriteRes<WriteFCvtF64ToI32, []>;
311*0fca6ea1SDimitry Andricdef : WriteRes<WriteFCvtF64ToI64, []>;
312*0fca6ea1SDimitry Andricdef : WriteRes<WriteFCvtF32ToF64, []>;
313*0fca6ea1SDimitry Andricdef : WriteRes<WriteFCvtF64ToF32, []>;
314*0fca6ea1SDimitry Andricdef : WriteRes<WriteFClass64, []>;
315*0fca6ea1SDimitry Andricdef : WriteRes<WriteFCmp64, []>;
316*0fca6ea1SDimitry Andricdef : WriteRes<WriteFMovF64ToI64, []>;
317*0fca6ea1SDimitry Andricdef : WriteRes<WriteFMovI64ToF64, []>;
318*0fca6ea1SDimitry Andricdef : WriteRes<WriteFMul64, []>;
319*0fca6ea1SDimitry Andricdef : WriteRes<WriteFMA64, []>;
320*0fca6ea1SDimitry Andricdef : WriteRes<WriteFDiv64, []>;
321*0fca6ea1SDimitry Andricdef : WriteRes<WriteFSqrt64, []>;
322*0fca6ea1SDimitry Andric
323*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFAdd64, 0>;
324*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFMul64, 0>;
325*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFMA64, 0>;
326*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFMA64Addend, 0>;
327*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFDiv64, 0>;
328*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFSqrt64, 0>;
329*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFCmp64, 0>;
330*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFSGNJ64, 0>;
331*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFMinMax64, 0>;
332*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFCvtF64ToI32, 0>;
333*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFCvtF64ToI64, 0>;
334*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFCvtI32ToF64, 0>;
335*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFCvtI64ToF64, 0>;
336*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFCvtF32ToF64, 0>;
337*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFCvtF64ToF32, 0>;
338*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFMovF64ToI64, 0>;
339*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFMovI64ToF64, 0>;
340*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadFClass64, 0>;
341*0fca6ea1SDimitry Andric} // Unsupported = true
342*0fca6ea1SDimitry Andric}
343*0fca6ea1SDimitry Andric
344bdd1243dSDimitry Andricmulticlass UnsupportedSchedSFB {
345bdd1243dSDimitry Andriclet Unsupported = true in {
346bdd1243dSDimitry Andricdef : WriteRes<WriteSFB, []>;
347bdd1243dSDimitry Andric
34806c3fb27SDimitry Andricdef : ReadAdvance<ReadSFBJmp, 0>;
34906c3fb27SDimitry Andricdef : ReadAdvance<ReadSFBALU, 0>;
35006c3fb27SDimitry Andric} // Unsupported = true
35106c3fb27SDimitry Andric}
35206c3fb27SDimitry Andric
35306c3fb27SDimitry Andricmulticlass UnsupportedSchedZfa {
35406c3fb27SDimitry Andriclet Unsupported = true in {
35506c3fb27SDimitry Andricdef : WriteRes<WriteFRoundF16, []>;
35606c3fb27SDimitry Andricdef : WriteRes<WriteFRoundF32, []>;
35706c3fb27SDimitry Andricdef : WriteRes<WriteFRoundF64, []>;
35806c3fb27SDimitry Andricdef : WriteRes<WriteFLI16, []>;
35906c3fb27SDimitry Andricdef : WriteRes<WriteFLI32, []>;
36006c3fb27SDimitry Andricdef : WriteRes<WriteFLI64, []>;
36106c3fb27SDimitry Andric
36206c3fb27SDimitry Andricdef : ReadAdvance<ReadFRoundF32, 0>;
36306c3fb27SDimitry Andricdef : ReadAdvance<ReadFRoundF64, 0>;
36406c3fb27SDimitry Andricdef : ReadAdvance<ReadFRoundF16, 0>;
365bdd1243dSDimitry Andric} // Unsupported = true
366bdd1243dSDimitry Andric}
367bdd1243dSDimitry Andric
368*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedZabha {
369*0fca6ea1SDimitry Andriclet Unsupported = true in {
370*0fca6ea1SDimitry Andricdef : WriteRes<WriteAtomicB, []>;
371*0fca6ea1SDimitry Andricdef : WriteRes<WriteAtomicH, []>;
372*0fca6ea1SDimitry Andric
373*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadAtomicBA, 0>;
374*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadAtomicBD, 0>;
375*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadAtomicHA, 0>;
376*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadAtomicHD, 0>;
377*0fca6ea1SDimitry Andric} // Unsupported = true
378*0fca6ea1SDimitry Andric}
379*0fca6ea1SDimitry Andric
380*0fca6ea1SDimitry Andricmulticlass UnsupportedSchedA {
381*0fca6ea1SDimitry Andriclet Unsupported = true in {
382*0fca6ea1SDimitry Andricdef : WriteRes<WriteAtomicW, []>;
383*0fca6ea1SDimitry Andricdef : WriteRes<WriteAtomicD, []>;
384*0fca6ea1SDimitry Andricdef : WriteRes<WriteAtomicLDW, []>;
385*0fca6ea1SDimitry Andricdef : WriteRes<WriteAtomicLDD, []>;
386*0fca6ea1SDimitry Andricdef : WriteRes<WriteAtomicSTW, []>;
387*0fca6ea1SDimitry Andricdef : WriteRes<WriteAtomicSTD, []>;
388*0fca6ea1SDimitry Andric
389*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadAtomicWA, 0>;
390*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadAtomicWD, 0>;
391*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadAtomicDA, 0>;
392*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadAtomicDD, 0>;
393*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadAtomicLDW, 0>;
394*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadAtomicLDD, 0>;
395*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadAtomicSTW, 0>;
396*0fca6ea1SDimitry Andricdef : ReadAdvance<ReadAtomicSTD, 0>;
397*0fca6ea1SDimitry Andric} // Unsupported = true
398*0fca6ea1SDimitry Andric}
399*0fca6ea1SDimitry Andric
400fe6060f1SDimitry Andric// Include the scheduler resources for other instruction extensions.
401bdd1243dSDimitry Andricinclude "RISCVScheduleZb.td"
4026e75b2fbSDimitry Andricinclude "RISCVScheduleV.td"
403*0fca6ea1SDimitry Andricinclude "RISCVScheduleXSf.td"
404*0fca6ea1SDimitry Andricinclude "RISCVScheduleZvk.td"
405