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/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
H A Disel-anyext-pair.ll17 %v7 = shl <64 x i32> %v6, <i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i3
[all...]
H A Disel-const-splat-imm.ll20 %v2 = shl <8 x i32> %v1, <i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24>
21 %v3 = ashr exact <8 x i32> %v2, <i32 24, i32 24, i3
[all...]
H A Dnon-simple-hvx-type.ll4 ; Check that <24 x i32> is treated as an HVX vector type.
6 define <24 x i32> @f0(ptr %a0, <24 x i32> %a1, <24 x i32> %a2) #0 {
13 %v1 = icmp ne <24 x i32> %a1, zeroinitializer
14 %v2 = call <24 x i32> @llvm.masked.load.v24i1.p0(ptr %a0, i32 4, <24 x i1> %v1, <24 x i32> undef)
15 ret <24 x i32> %v2
18 declare <24
[all...]
/llvm-project/mlir/test/Dialect/Linalg/
H A Dtransform-op-hoist-pad-build-packing-loop-nest.mlir6 %arg0: tensor<24x12xf32>, %arg1: tensor<12x25xf32>, %arg2: tensor<24x25xf32>)
7 -> tensor<24x25xf32>
9 %0 = linalg.matmul ins(%arg0, %arg1 : tensor<24x12xf32>, tensor<12x25xf32>) outs(%arg2 : tensor<24x25xf32>) -> tensor<24x25xf32>
10 func.return %0 : tensor<24x25xf32>
40 %arg0: tensor<24x12xf32>, %arg1: tensor<12x25xf32>, %arg2: tensor<24x25xf32>)
41 -> tensor<24x25xf3
[all...]
H A Dtransform-op-hoist-pad.mlir4 %arg0: tensor<24x12xf32>, %arg1: tensor<12x25xf32>, %arg2: tensor<24x25xf32>)
5 -> tensor<24x25xf32>
8 %0 = linalg.matmul ins(%arg0, %arg1 : tensor<24x12xf32>, tensor<12x25xf32>) outs(%arg2 : tensor<24x25xf32>) -> tensor<24x25xf32>
9 func.return %0 : tensor<24x25xf32>
42 %arg0: tensor<24x12xf32>, %arg1: tensor<12x25xf32>, %arg2: tensor<24x25xf32>)
43 -> tensor<24x25xf3
[all...]
H A Dtransform-op-vectorize.mlir4 // CHECK-SAME: %[[A:.*]]: tensor<24x12xf32>
6 // CHECK-SAME: %[[C:.*]]: tensor<24x25xf32>
7 func.func @vectorize_matmul(%arg0: tensor<24x12xf32>,
9 %arg2: tensor<24x25xf32>) -> tensor<24x25xf32> {
15 …inalg.matmul ins(%arg0, %arg1 : tensor<24x12xf32>, tensor<12x25xf32>) outs(%arg2 : tensor<24x25xf3…
16 func.return %0 : tensor<24x25xf32>
31 // CHECK-SAME: %[[A:.*]]: memref<24x12xf32>
33 // CHECK-SAME: %[[C:.*]]: memref<24x25xf32>
34 func.func @vectorize_matmul_memref(%arg0: memref<24x12xf32>,
36 %arg2: memref<24x25xf32>) {
[all …]
H A Dtransform-op-pad.mlir6 func.func @static_sizes_output_divisible(%arg0: tensor<24x12xf32>,
8 %arg2: tensor<24x25xf32>,
9 %iv0 : index, %iv1 : index, %iv2 : index) -> tensor<24x25xf32> {
15 %1 = tensor.extract_slice %arg0[%iv0, %iv2] [4, %0] [1, 1] : tensor<24x12xf32> to tensor<4x?xf32>
17 %3 = tensor.extract_slice %arg2[%iv0, %iv1] [4, 5] [1, 1] : tensor<24x25xf32> to tensor<4x5xf32>
32 %5 = tensor.insert_slice %4 into %arg2[%iv0, %iv1] [4, 5] [1, 1] : tensor<4x5xf32> into tensor<24x25xf32>
33 func.return %5 : tensor<24x25xf32>
56 func.func @pad_to_multiple(%arg0: tensor<24x12xf32>,
58 %arg2: tensor<24x25xf32>,
59 %iv0 : index, %iv1 : index, %iv2 : index) -> tensor<24x25xf3
[all...]
/llvm-project/llvm/test/MC/Mips/msa/
H A Dinvalid.s26 binsli.b $w1, $w2, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
27 binsli.b $w1, $w2, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
28 binsli.h $w1, $w2, -1 # CHECK: :[[@LINE]]:24: error: expected 4-bit unsigned immediate
29 binsli.h $w1, $w2, 16 # CHECK: :[[@LINE]]:24: error: expected 4-bit unsigned immediate
30 binsli.w $w1, $w2, -1 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
31 binsli.w $w1, $w2, 32 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
32 binsli.d $w1, $w2, -1 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate
33 binsli.d $w1, $w2, 64 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate
34 binsri.b $w1, $w2, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
35 binsri.b $w1, $w2, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
[all …]
/llvm-project/libcxx/test/libcxx/algorithms/alg.sorting/assert.sort.invalid_comparator/
H A Dbad_comparator_values.h106 0 24 1
165 1 24 1
224 2 24 1
283 3 24 1
342 4 24 1
401 5 24 1
460 6 24 1
519 7 24 1
578 8 24 1
637 9 24 1
[all …]
/llvm-project/clang/test/Preprocessor/
H A Dsuggest-typoed-directive.c44 // CHECK: fix-it:{{.*}}:{[[@LINE-24]]:2-[[@LINE-24]]:4}:"if"
45 // CHECK: fix-it:{{.*}}:{[[@LINE-24]]:2-[[@LINE-24]]:5}:"if"
46 // CHECK: fix-it:{{.*}}:{[[@LINE-24]]:2-[[@LINE-24]]:6}:"ifdef"
47 // CHECK: fix-it:{{.*}}:{[[@LINE-24]]:3-[[@LINE-24]]:6}:"elif"
48 // CHECK: fix-it:{{.*}}:{[[@LINE-24]]:4-[[@LINE-24]]:9}:"elif"
49 // CHECK: fix-it:{{.*}}:{[[@LINE-24]]:2-[[@LINE-24]]:8}:"elif"
50 // CHECK: fix-it:{{.*}}:{[[@LINE-24]]:2-[[@LINE-24]]:9}:"elifdef"
51 // CHECK: fix-it:{{.*}}:{[[@LINE-24]]:2-[[@LINE-24]]:10}:"elifdef"
52 // CHECK: fix-it:{{.*}}:{[[@LINE-24]]:2-[[@LINE-24]]:11}:"elifndef"
53 // CHECK: fix-it:{{.*}}:{[[@LINE-24]]:2-[[@LINE-24]]:5}:"else"
[all …]
/llvm-project/bolt/test/X86/Inputs/
H A Dunreachable.s22 subq $24, %rsp
23 movq %rdi, -24(%rbp)
24 incq -24(%rbp)
27 .L1: incq -24(%rbp)
28 cmpq $2,-24(%rbp)
32 .L3: incq -24(%rbp)
33 .L4: incq -24(%rbp)
34 movq -24(%rbp), %rax
46 incq -24(%rbp)
49 .LP1: incq -24(%rbp)
[all …]
/llvm-project/llvm/test/CodeGen/Hexagon/
H A Dsignext-inreg.ll33 %shl = shl <2 x i32> %m, <i32 24, i32 24>
34 %shr = ashr exact <2 x i32> %shl, <i32 24, i32 24>
62 ; CHECK-NEXT: r11:10 = memd(r29+#24)
87 ; CHECK-NEXT: memd(r0+#24) = r7:6
104 ; CHECK-64B-NEXT: r0 = #24
118 ; CHECK-128B-NEXT: r0 = #24
128 %shl = shl <16 x i32> %m, <i32 24, i32 24, i3
[all...]
H A Dearly-if.ll8 %struct.2 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24
[all...]
H A Dcommon-gep-icm.ll9 %struct.2 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24
[all...]
H A Dprof-early-if.ll7 %s.0 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24
[all...]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Darm64-tls-local-exec.ll4 …einstrs -show-mc-encoding -code-model=tiny -tls-size=24 < %s | FileCheck %s --check-prefix=CHECK-24
5 … -filetype=obj < %s -code-model=tiny -tls-size=24 | llvm-objdump -r - | FileCheck --check-prefix=C…
14 …einstrs -show-mc-encoding -code-model=tiny -tls-size=32 < %s | FileCheck %s --check-prefix=CHECK-24
15 …< %s -code-model=tiny -tls-size=32 | llvm-objdump -r - | FileCheck --check-prefix=CHECK-24-RELOC %s
20 …-none-linux-gnu -verify-machineinstrs -show-mc-encoding < %s | FileCheck --check-prefix=CHECK-24 %s
21 …-none-linux-gnu -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-24-RELOC %s
22 …verify-machineinstrs -show-mc-encoding -code-model=tiny < %s | FileCheck %s --check-prefix=CHECK-24
23 …filetype=obj < %s -code-model=tiny | llvm-objdump -r - | FileCheck --check-prefix=CHECK-24-RELOC %s
24 …erify-machineinstrs -show-mc-encoding -code-model=small < %s | FileCheck %s --check-prefix=CHECK-24
25 …iletype=obj < %s -code-model=small | llvm-objdump -r - | FileCheck --check-prefix=CHECK-24-RELOC %s
[all …]
/llvm-project/mlir/test/Dialect/XeGPU/
H A DXeGPUOps.mlir9 // CHECK: gpu.func @test_create_nd_tdesc_vc_1(%[[arg0:.*]]: memref<24x32xf32>) {
10 gpu.func @test_create_nd_tdesc_vc_1(%src: memref<24x32xf32>) {
11 // CHECK: %[[REG:.*]] = xegpu.create_nd_tdesc %arg0[0, 0] : memref<24x32xf32> -> !xegpu.tensor_desc<8x16xf32>
12 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> -> !xegpu.tensor_desc<8x16xf32>
16 // CHECK: gpu.func @test_create_nd_tdesc_with_sg_map(%[[arg0:.*]]: memref<24x32xf32>) {
17 gpu.func @test_create_nd_tdesc_with_sg_map(%src: memref<24x32xf32>) {
18 // CHECK: %[[REG:.*]] = xegpu.create_nd_tdesc %arg0[0, 0] : memref<24x32xf32> -> !xegpu.tensor_desc<8x16xf32, #xegpu.sg_map<wi_layout = [1, 16], wi_data = [1, 1]>>
19 %1 = xegpu.create_nd_tdesc %src[0, 0] : memref<24x32xf32> ->
33 // CHECK: gpu.func @test_create_nd_tdesc_vc_3(%[[arg0:.*]]: memref<24x32xf32>) {
34 gpu.func @test_create_nd_tdesc_vc_3(%src: memref<24x32xf3
[all...]
/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dcommon_entry_exit_abi2.S35 // Save r17:16 at fp+#-8, r19:18 at fp+#-16, r21:20 at fp+#-24, r23:22 at
36 // fp+#-32, r25:24 at fp+#-40, and r27:26 at fp+#-48.
43 memd(fp+#-40) = r25:24
47 memd(fp+#-24) = r21:20
58 memd(fp+#-40) = r25:24
62 memd(fp+#-24) = r21:20
74 memd(fp+#-24) = r21:20
85 memd(fp+#-24) = r21:20
118 r25:24 = memd(fp+#-40)
122 r21:20 = memd(fp+#-24)
[all …]
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dstore-forward-be32.ll19 ; CHECK-NEXT: srwi 3, 3, 24
20 ; CHECK-NEXT: stw 4, 24(1)
35 ; CHECK-NEXT: stw 4, 24(1)
48 ; CHECK-NEXT: srawi 3, 3, 24
49 ; CHECK-NEXT: stw 4, 24(1)
64 ; CHECK-NEXT: stw 4, 24(1)
77 ; CHECK-NEXT: srwi 3, 3, 24
78 ; CHECK-NEXT: stw 4, 24(1)
91 ; CHECK-NEXT: srawi 3, 3, 24
92 ; CHECK-NEXT: stw 4, 24(
[all...]
/llvm-project/llvm/test/DebugInfo/MIR/X86/
H A Ddebug-call-site-param.mir88 call void @llvm.dbg.value(metadata i32 %call, metadata !18, metadata !DIExpression()), !dbg !24
89 store i32 %call, ptr %local1, align 4, !dbg !24
90 %add = add nsw i32 %arg3, 3, !dbg !24
91 %add1 = add nsw i32 %arg2, %arg1, !dbg !24
92 … @llvm.dbg.value(metadata ptr %local1, metadata !18, metadata !DIExpression(DW_OP_deref)), !dbg !24
93 call void @foo(ptr nonnull %local1, i32 %arg2, i32 10, i32 15, i32 %add, i32 %add1), !dbg !24
94 ret void, !dbg !24
127 !20 = !DILocation(line: 4, column: 24, scope: !10)
131 !24 = !DILocation(line: 5, column: 7, scope: !10)
159 CFI_INSTRUCTION def_cfa_offset 24
[all …]
/llvm-project/clang/test/CodeGen/aarch64-sve-intrinsics/
H A Dacle_sve_set3-bfloat.c
H A Dacle_sve_ld3-bfloat.c
/llvm-project/libcxx/test/libcxx/strings/basic.string/
H A Dsizeof.compile.pass.cpp63 static_assert(sizeof(std::string) == 24, "");
64 static_assert(sizeof(min_string<char>) == 24, "");
70 static_assert(sizeof(std::wstring) == 24, "");
71 static_assert(sizeof(min_string<wchar_t>) == 24, "");
75 static_assert(sizeof(std::wstring) == 24, "");
76 static_assert(sizeof(min_string<wchar_t>) == 24, "");
85 static_assert(sizeof(std::u8string) == 24, "");
86 static_assert(sizeof(min_string<char8_t>) == 24, "");
92 static_assert(sizeof(std::u16string) == 24, "");
93 static_assert(sizeof(std::u32string) == 24, "");
[all...]
/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
H A Dcall.ll10 ; MIPS32-NEXT: addiu $sp, $sp, -24
11 ; MIPS32-NEXT: .cfi_def_cfa_offset 24
20 ; MIPS32-NEXT: addiu $sp, $sp, 24
28 ; MIPS32_PIC-NEXT: addiu $sp, $sp, -24
29 ; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 24
40 ; MIPS32_PIC-NEXT: addiu $sp, $sp, 24
69 ; MIPS32-NEXT: addiu $sp, $sp, -24
70 ; MIPS32-NEXT: .cfi_def_cfa_offset 24
79 ; MIPS32-NEXT: addiu $sp, $sp, 24
87 ; MIPS32_PIC-NEXT: addiu $sp, $sp, -24
[all …]
/llvm-project/llvm/test/CodeGen/ARM/
H A Dsignext-inreg.ll9 ; CHECK-NEXT: vshl.i32 q8, q8, #24
10 ; CHECK-NEXT: vshr.s32 q8, q8, #24
15 %shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24>
16 %shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>

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