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/llvm-project/llvm/test/CodeGen/AArch64/
H A D	regalloc-last-chance-recolor-with-split.mir	95 - { id: 2, class: gpr32, preferred-register: '' } 271 ; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000) 277 ; CHECK-NEXT: dead $w2 = MOVi32imm 2, implicit-def $x2 278 ; CHECK-NEXT: renamable $w19 = MOVi32imm 2, implicit-def $x19 279 …2, 0, 2, 4, 2, 39, 2, 0, 2, 1, 2, 0, 2, 42, 2, 2, 2, 14, 2, 0, 2, 3, 2, 400, 2, 3, 2, 400, 2, 0, 1… 284 …2, 4, 1, undef renamable $x0, undef $x0, 2, 0, 2, 4, 2, 35, 2, 0, 2, 2, 2, 0, 2, 48, 2, 0, 2, 14, … 288 …2, 4, 2, undef renamable $x0, undef $x0, $w1, 2, 0, 2, 0, 2, 41, 2, 0, 2, 2, 2, 0, 2, 73, 2, 3, 2,… 291 …2, 4, 2, undef renamable $x0, undef $x0, undef $w1, 2, 0, 2, 0, 2, 39, 2, 0, 2, 2, 2, 0, 2, 78, 2,… 294 …2, 4, 2, undef renamable $x0, undef $x0, undef $w1, 2, 0, 2, 0, 2, 37, 2, 0, 2, 2, 2, 0, 2, 83, 2,… 297 …2, 4, 1, undef renamable $x0, undef $w0, 2, 0, 2, 0, 2, 35, 2, 0, 2, 2, 2, 0, 2, 95, 2, 0, 2, 14, … [all …]
H A D	complex-deinterleaving-add-mull-fixed-contract.ll	`10 ; CHECK-NEXT: zip2 v4.2d, v2.2d, v3.2d 11 ; CHECK-NEXT: zip2 v5.2d, v0.2d, v1.2d 12 ; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d 13 ; CHECK-NEXT: zip1 v2.2d, v2.2d, v3.2d 14 ; CHECK-NEXT: fmul v1.2d, v5.2d, v4.2d 15 ; CHECK-NEXT: fmul v3.2d, v0.2d, v4.2d 16 ; CHECK-NEXT: fneg v1.2d, v1.2d 17 ; CHECK-NEXT: fmla v3.2d, v2.2d, v5.2d 18 ; CHECK-NEXT: fmla v1.2d, v2.2d, v0.2d 19 ; CHECK-NEXT: fadd v1.2d, v2.2d, v1.2d [all …]`
H A D	complex-deinterleaving-multiuses.ll	11 ; CHECK-NEXT: movi v3.2d, #0000000000000000 12 ; CHECK-NEXT: movi v2.2d, #0000000000000000 21 %strided.vec = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2> 22 %strided.vec35 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3> 23 %strided.vec37 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2> 24 %strided.vec38 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3> 25 %0 = fmul fast <2 x float> %strided.vec37, %strided.vec 26 %1 = fmul fast <2 x float> %strided.vec38, %strided.vec35 27 %2 = fsub fast <2 x float> %0, %1 28 %3 = fmul fast <2 x float> %2, %strided.vec35 [all …]
H A D	complex-deinterleaving-mixed-cases.ll	10 ; CHECK-NEXT: movi v4.2d, #0000000000000000 11 ; CHECK-NEXT: movi v3.2d, #0000000000000000 19 %strided.vec = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2> 20 %strided.vec151 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3> 21 %strided.vec153 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2> 22 %strided.vec154 = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3> 23 %0 = fmul fast <2 x float> %strided.vec154, %strided.vec151 24 %1 = fmul fast <2 x float> %strided.vec153, %strided.vec 25 %2 = fmul fast <2 x float> %strided.vec154, %strided.vec 26 %3 = fmul fast <2 x float> %strided.vec153, %strided.vec151 [all …]
H A D	complex-deinterleaving-add-mull-fixed-fast.ll	10 ; CHECK-NEXT: fcmla v4.2d, v0.2d, v2.2d, #0 11 ; CHECK-NEXT: fcmla v5.2d, v1.2d, v3.2d, #0 12 ; CHECK-NEXT: fcmla v4.2d, v0.2d, v2.2d, #90 13 ; CHECK-NEXT: fcmla v5.2d, v1.2d, v3.2d, #90 18 %strided.vec = shufflevector <4 x double> %a, <4 x double> poison, <2 x i32> <i32 0, i32 2> 19 %strided.vec28 = shufflevector <4 x double> %a, <4 x double> poison, <2 x i32> <i32 1, i32 3> 20 %strided.vec30 = shufflevector <4 x double> %b, <4 x double> poison, <2 x i32> <i32 0, i32 2> 21 %strided.vec31 = shufflevector <4 x double> %b, <4 x double> poison, <2 x i32> <i32 1, i32 3> 22 %0 = fmul fast <2 x double> %strided.vec31, %strided.vec 23 %1 = fmul fast <2 x double> %strided.vec30, %strided.vec28 [all …]
/llvm-project/llvm/test/CodeGen/X86/
H A D	keylocker-intrinsics-fast-isel.ll	6 define void @test_loadiwkey(i32 %ctl, <2 x i64> %intkey, <2 x i64> %enkey_lo, <2 x i64> %enkey_hi) { 13 …tail call void @llvm.x86.loadiwkey(<2 x i64> %intkey, <2 x i64> %enkey_lo, <2 x i64> %enkey_hi, i3… 17 define i32 @test_encodekey128_u32(i32 %htype, <2 x i64> %key, ptr nocapture %h) { 29 …%0 = tail call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86… 30 %1 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 1 31 store <2 x i64> %1, ptr %h, align 1 32 %2 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 2 34 store <2 x i64> %2, ptr %3, align 1 35 %4 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 3 37 store <2 x i64> %4, ptr %5, align 1 [all …]
H A D	splat-for-size.ll	`9 define <2 x double> @splat_v2f64(<2 x double> %x) #0 { 16 %add = fadd <2 x double> %x, <double 1.0, double 1.0> 17 ret <2 x double> %add 20 define <2 x double> @splat_v2f64_pgso(<2 x double> %x) !prof !14 { 27 %add = fadd <2 x double> %x, <double 1.0, double 1.0> 28 ret <2 x double> %add 93 define <2 x i64> @splat_v2i64(<2 x i64> %x) #1 { 96 ; AVX-NEXT: vmovddup {{.#+}} xmm1 = [2,2] 103 ; AVX2-NEXT: vpbroadcastq {{.#+}} xmm1 = [2,2] 106 %add = add <2 x i64> %x, <i64 2, i64 2> [all …]`
H A D	statepoint-invoke-ra-remove-back-copies.mir	3 # RUN: llc -x mir -run-pass=greedy -verify-machineinstrs < %s 2>&1 \| FileCheck %s 13 …2, i32 5, ptr nonnull elementtype(void (ptr addrspace(1), ptr addrspace(1))) @quux, i32 2, i32 0, … 42 …2, i32 12, i32 0, i32 3, i32 1, i32 0, ptr addrspace(1) %tmp11, i32 0, ptr addrspace(1) %tmp11, i3… 62 …2, i32 3, i32 0, i32 0) [ "deopt"(i32 0, i32 10, i32 0, i32 10, i32 0, i32 4, i32 1, i32 7, ptr nu… 74 …2, i32 -39, i32 0, i32 0) [ "deopt"(i32 0, i32 10, i32 0, i32 10, i32 0, i32 4, i32 1, i32 7, ptr … 85 …ace(1) %tmp30, i32 7, ptr null, i32 0, ptr addrspace(1) %tmp30, i32 10, i32 2, i32 19, i32 0, i32 … 93 …2, i32 10, i32 0, i32 0) [ "deopt"(i32 0, i32 10, i32 0, i32 10, i32 0, i32 4, i32 1, i32 7, ptr n… 100 …2, i32 3, i32 0, i32 0) [ "deopt"(i32 0, i32 10, i32 0, i32 10, i32 0, i32 4, i32 1, i32 7, ptr nu… 105 …2, i32 10, i32 0, i32 0) [ "deopt"(i32 0, i32 10, i32 0, i32 10, i32 0, i32 4, i32 1, i32 7, ptr n… 141 - { id: 2, class: gr64, preferred-register: '' } [all …]
H A D	statepoint-invoke-ra-inline-spiller.mir	14 …2, i32 5, ptr nonnull elementtype(void (ptr addrspace(1), ptr addrspace(1))) @quux, i32 2, i32 0, … 30 …2, i32 5, ptr nonnull elementtype(void (ptr addrspace(1), i32, i32, ptr addrspace(1), i32)) @hoge.… 33 …dcc ptr addrspace(1) @llvm.experimental.gc.relocate.p1(token %tmp14, i32 2, i32 2) ; (%tmp4, %tmp4) 48 …2, i32 0, i32 43, i32 0, i32 2, i32 0, i32 7, ptr null, i32 7, ptr null, i32 10, i32 1, i32 10, i3… 55 call void @barney() #2 63 …2, i32 3, i32 0, i32 0) [ "deopt"(i32 0, i32 2, i32 0, i32 43, i32 0, i32 2, i32 0, i32 7, ptr nul… 88 attributes #2 = { nounwind } 104 - { id: 2, class: gr64, preferred-register: '' } 210 …2, 5, 2, undef %24:gr64, $rdi, undef $rsi, 2, 0, 2, 0, 2, 37, 2, 0, 2, 2, 2, 0, 2, 43, 2, 0, 2, 2,… 219 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) [all …]
H A D	keylocker-intrinsics.ll	7 declare void @llvm.x86.loadiwkey(<2 x i64>, <2 x i64>, <2 x i64>, i32) 8 declare { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodek… 9 declare { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.… 10 declare { i8, <2 x i64> } @llvm.x86.aesenc128kl(<2 x i64>, ptr) 11 declare { i8, <2 x i64> } @llvm.x86.aesdec128kl(<2 x i64>, ptr) 12 declare { i8, <2 x i64> } @llvm.x86.aesenc256kl(<2 x i64>, ptr) 13 declare { i8, <2 x i64> } @llvm.x86.aesdec256kl(<2 x i64>, ptr) 14 …2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.… 15 …2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.… 16 …2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.… [all …]
H A D	statepoint-invoke-ra-enter-at-end.mir	2 # RUN: llc -x mir -o - %s -run-pass=greedy -verify-regalloc 2>&1 \| FileCheck %s 19 …2, i32 5, ptr nonnull elementtype(void ()) @wibble, i32 0, i32 0, i32 0, i32 0) [ "deopt"(i32 0, i… 21 …2, i32 0, i32 0, i32 0, i32 1, i32 0, i32 7, ptr null, i32 9, i32 1, i32 9, i32 0, i32 5, i32 1, i… 23 …2, i32 5, ptr addrspace(1) ()* nonnull elementtype(ptr addrspace(1) ()) @blam, i32 0, i32 0, i32 0… 36 …2, i32 0, i32 0, i32 0, i32 1, i32 0, i32 7, ptr null, i32 2, i32 1, i32 71, i32 0, i32 5, i32 0, … 42 …2, i32 0, i32 %tmp19, ptr addrspace(1) nonnull undef, i32 0, i32 0) [ "deopt"(i32 0, i32 2, i32 0,… 53 …2, i32 5, ptr nonnull elementtype(void (ptr addrspace(1))) @baz, i32 1, i32 0, ptr addrspace(1) un… 54 …c ptr addrspace(1) @llvm.experimental.gc.relocate.p1(token %tmp29, i32 1, i32 2) ; (%tmp23, %tmp23) 86 …2, i32 5, ptr nonnull elementtype(void (ptr addrspace(1))) @baz, i32 1, i32 0, ptr addrspace(1) %t… 93 …c ptr addrspace(1) @llvm.experimental.gc.relocate.p1(token %tmp60, i32 1, i32 2) ; (%tmp13, %tmp13) [all …]
/llvm-project/llvm/test/CodeGen/MSP430/
H A D	BranchSelector.ll	`5 @reg = common global i16 0, align 2 12 store volatile i16 11, ptr @reg, align 2 13 store volatile i16 13, ptr @reg, align 2 14 store volatile i16 17, ptr @reg, align 2 15 store volatile i16 11, ptr @reg, align 2 16 store volatile i16 13, ptr @reg, align 2 17 store volatile i16 17, ptr @reg, align 2 18 store volatile i16 11, ptr @reg, align 2 19 store volatile i16 13, ptr @reg, align 2 20 store volatile i16 17, ptr @reg, align 2 [all...]`
/llvm-project/llvm/test/Analysis/CostModel/ARM/
H A D	divrem.ll	2 ; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv7-apple-ios6.0.0 -mcpu=cortex-a9 \| FileCheck %s --check-prefix=CHECK-NEON 3 ; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s \| FileCheck %s --check-prefix=CHECK-MVE 4 ; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8m.main-none-eabi < %s \| FileCheck %s --check-prefix=CHECK-V8M-MAIN 5 ; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=thumbv8m.base-none-eabi < %s \| FileCheck %s --check-prefix=CHECK-V8M-BASE 6 ; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=armv8r-none-eabi -mattr=+neon,+fp-armv8 < %s \| FileCheck %s --check-prefix=CHECK-V8R 12 ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = sdiv i8 undef, undef 13 ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = udiv i8 undef, undef 16 ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %5 = sdiv i8 undef, 2 [all...]
/llvm-project/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A D	asimd-st1.s	`7 st1 {v0.2s}, [sp] 8 st1 {v0.2s, v1.2s}, [sp] 9 st1 {v0.2s, v1.2s, v2.2s}, [sp] 10 st1 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp] 13 st1 {v0.2d}, [sp] 14 st1 {v0.2d, v1.2d}, [sp] 15 st1 {v0.2d, v1.2d, v2.2d}, [sp] 16 st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp] 19 st1 {v0.2s}, [sp], #8 20 st1 {v0.2s, v1.2s}, [sp], #16 [all …]`
H A D	asimd-ld1.s	`7 ld1r {v0.2s}, [sp] 8 ld1 {v0.2s}, [sp] 9 ld1 {v0.2s, v1.2s}, [sp] 10 ld1 {v0.2s, v1.2s, v2.2s}, [sp] 11 ld1 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp] 14 ld1r {v0.2d}, [sp] 15 ld1 {v0.2d}, [sp] 16 ld1 {v0.2d, v1.2d}, [sp] 17 ld1 {v0.2d, v1.2d, v2.2d}, [sp] 18 ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp] [all …]`
H A D	asimd-ld4.s	`7 ld4r {v0.2s, v1.2s, v2.2s, v3.2s}, [sp] 8 ld4 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp] 11 ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [sp] 12 ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp] 15 ld4r {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], #16 16 ld4 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], #32 19 ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #32 20 ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #64 23 ld4r {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], x0 24 ld4 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], x0 [all …]`
/llvm-project/llvm/test/Analysis/CostModel/AMDGPU/
H A D	shufflevector.ll	2 ; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1010 -S \| FileCheck -check-prefixes=ALL,GFX9-10 %s 3 ; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -S \| FileCheck -check-prefixes=ALL,GFX9-10 %s 4 ; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=fiji -S \| FileCheck -check-prefixes=ALL,VI %s 5 ; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1010 -cost-kind=code-size -S \| FileCheck -check-prefixes=ALL-SIZE,GFX9-10-SIZE %s 6 ; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -cost-kind=code-size -S \| FileCheck -check-prefixes=ALL-SIZE,GFX9-10-SIZE %s 7 ; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=fiji -cost-kind=code-size -S \| FileCheck -check-prefixes=ALL-SIZE,VI-SIZE %s 10 define amdgpu_kernel void @shufflevector_i16(<2 x i16> %vec1, <2 x i16> %vec2) { 12 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %shuf00 = shufflevector <2 x i16> %vec1, <2 [all...]
/llvm-project/llvm/test/Analysis/ScalarEvolution/
H A D	pr58402-large-number-of-zext-exprs.ll	2 ; RUN: opt -passes='print<scalar-evolution>' -disable-output %s 2>&1 \| FileCheck %s 14 ; CHECK-NEXT: --> (zext i1 %cmp to i32) U: [0,2) S: [0,2) Exits: <<Unknown>> LoopDispositions: {… 15 ; CHECK-NEXT: %i = and i32 %conv, -2 16 ; CHECK-NEXT: --> (2 * ((zext i1 %cmp to i32) /u 2))<nuw><nsw> U: [0,1) S: [0,1) Exits: <<Unknow… 18 ; CHECK-NEXT: --> (4 + (2 * ((zext i1 %cmp to i32) /u 2))<nuw><nsw>)<nuw><nsw> U: [4,5) S: [4,5)… 19 ; CHECK-NEXT: %i1 = and i32 %add7, -2 20 ; CHECK-NEXT: --> (2 * ((4 + (2 * ((zext i1 %cmp to i32) /u 2))<nuw><nsw>)<nuw><nsw> /u 2))<nuw>… 22 ; CHECK-NEXT: --> (4 + (2 * ((4 + (2 * ((zext i1 %cmp to i32) /u 2))<nuw><nsw>)<nuw><nsw> /u 2))… 23 ; CHECK-NEXT: %i2 = and i32 %add7.1, -2 24 ; CHECK-NEXT: --> (2 * ((4 + (2 * ((4 + (2 * ((zext i1 %cmp to i32) /u 2))<nuw><nsw>)<nuw><nsw> … [all …]
/llvm-project/llvm/test/Transforms/InstSimplify/
H A D	cmp-vec-fast-path.ll	`6 define <2 x i1> @i32cmp_eq_fixed_zero() { 8 ; CHECK-NEXT: ret <2 x i1> splat (i1 true) 10 %res = icmp eq <2 x i32> zeroinitializer, zeroinitializer 11 ret <2 x i1> %res 14 define <vscale x 2 x i1> @i32cmp_eq_scalable_zero() { 16 ; CHECK-NEXT: ret <vscale x 2 x i1> splat (i1 true) 18 %res = icmp eq <vscale x 2 x i32> zeroinitializer, zeroinitializer 19 ret <vscale x 2 x i1> %res 22 define <2 x i1> @i32cmp_eq_fixed_one() { 24 ; CHECK-NEXT: ret <2 [all...]`
/llvm-project/llvm/test/CodeGen/RISCV/rvv/
H A D	rvv-peephole-vmerge-masked-vops.ll	`4 declare <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i64); 5 declare <vscale x 2 x float> @llvm.riscv.vmerge.nxv2f32.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 [all...]`
H A D	rvv-peephole-vmerge-vops.ll	`4 declare <vscale x 2 x i16> @llvm.vp.merge.nxv2i16(<vscale x 2 x i1>, <vscale x 2 x i16>, <vscale x 2 x i16>, i32) 5 declare <vscale x 2 x i32> @llvm.vp.merge.nxv2i32(<vscale x 2 x i1>, <vscale x 2 x i32>, <vscale x 2 x i32>, i32) 6 declare <vscale x 2 x float> @llvm.vp.merge.nxv2f32(<vscale x 2 [all...]`
/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A D	forwarding-A57.s	`4 # CHECK: Instructions: 2 7 # CHECK: [0,0] DeeeeeER .. fmul v0.2s, v1.2s, v2.2s 8 # CHECK-NEXT: [0,1] DeeeeeeeeeER fmla v0.2s, v1.2s, v2.2s 11 # CHECK: Instructions: 2 17 # CHECK: [2] Code Region 18 # CHECK: Instructions: 2 21 # CHECK: [0,0] DeeeeeER .. fmulx v0.2s, v1.2s, v2.2s 22 # CHECK-NEXT: [0,1] DeeeeeeeeeER fmls v0.2s, v1.2s, v2.2s 25 # CHECK: Instructions: 2 32 # CHECK: Instructions: 2 [all …]`
/llvm-project/clang/test/CodeGen/X86/
H A D	keylocker.c	10 // CHECK64-NEXT: [[__INTKEY_ADDR_I:%.]] = alloca <2 x i64>, align 16 11 // CHECK64-NEXT: [[__ENKEY_LO_ADDR_I:%.]] = alloca <2 x i64>, align 16 12 // CHECK64-NEXT: [[__ENKEY_HI_ADDR_I:%.]] = alloca <2 x i64>, align 16 14 // CHECK64-NEXT: [[INTKEY_ADDR:%.]] = alloca <2 x i64>, align 16 15 // CHECK64-NEXT: [[ENKEY_LO_ADDR:%.]] = alloca <2 x i64>, align 16 16 // CHECK64-NEXT: [[ENKEY_HI_ADDR:%.]] = alloca <2 x i64>, align 16 18 // CHECK64-NEXT: store <2 x i64> [[INTKEY:%.]], ptr [[INTKEY_ADDR]], align 16 19 // CHECK64-NEXT: store <2 x i64> [[ENKEY_LO:%.]], ptr [[ENKEY_LO_ADDR]], align 16 20 // CHECK64-NEXT: store <2 x i64> [[ENKEY_HI:%.]], ptr [[ENKEY_HI_ADDR]], align 16 22 // CHECK64-NEXT: [[TMP1:%.]] = load <2 x i64>, ptr [[INTKEY_ADDR]], align 16 [all …]
/llvm-project/llvm/lib/Target/AArch64/
H A D	AArch64PerfectShuffle.h	23 // 3690 entries have cost 2 29 2080972802U, // <0,0,0,1>: Cost 2 ins <0,0,u,1>, lane 2 30 1679065190U, // <0,0,0,2>: Cost 2 vuzpl <0,2,0,2>, LHS 31 2085707777U, // <0,0,0,3>: Cost 2 ins <0,u,0,3>, lane 1 32 1476398390U, // <0,0,0,4>: Cost 2 vext1 <0,0,0,0>, RHS 33 2080440323U, // <0,0,0,5>: Cost 2 ins <0,0,0,u>, lane 3 34 2080440323U, // <0,0,0,6>: Cost 2 ins <0,0,0,u>, lane 3 35 2080440323U, // <0,0,0,7>: Cost 2 ins <0,0,0,u>, lane 3 37 1812774912U, // <0,0,1,0>: Cost 2 vzipl LHS, <0,0,0,0> 39 1812775076U, // <0,0,1,2>: Cost 2 vzipl LHS, <0,2,0,2> [all …]
/llvm-project/llvm/test/MC/AArch64/
H A D	neon-2velem.s	6 // Instructions with 2 vectors and an element 9 mla v0.2s, v1.2s, v2.s[2] 10 mla v0.2s, v1.2s, v22.s[2] 14 // CHECK: mla v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x08,0x82,0x2f] 15 // CHECK: mla v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x08,0x96,0x2f] 19 mla v0.4h, v1.4h, v2.h[2] 20 mla v0.4h, v1.4h, v15.h[2] 24 // CHECK: mla v0.4h, v1.4h, v2.h[2] // encoding: [0x20,0x00,0x62,0x2f] 25 // CHECK: mla v0.4h, v1.4h, v15.h[2] // encoding: [0x20,0x00,0x6f,0x2f] 29 mls v0.2s, v1.2s, v2.s[2] [all …]

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