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/freebsd-src/contrib/llvm-project/clang/include/clang/Basic/
H A DMSP430Target.def1 //===--- MSP430Target.def - MSP430 Feature/Processor Database----*- C++ -*
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRFixupKinds.h1 //===-- AVRFixupKinds.h - AVR Specific Fixup Entries ------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
27 /// A 32-bit AVR fixup.
30 /// A 7-bit PC-relative fixup for the family of conditional
31 /// branches which take 7-bit targets (BRNE,BRGT,etc).
33 /// A 12-bit PC-relative fixup for the family of branches
34 /// which take 12-bit targets (RJMP,RCALL,etc).
39 /// aligned to 2 bytes, so the 0'th bit is always 0.
40 /// This way there is 13-bits of precision.
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/freebsd-src/contrib/llvm-project/clang/lib/Headers/
H A Davxvnniint16intrin.h1 /*===----------- avxvnniint16intrin.h - AVXVNNIINT16 intrinsics-------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
27 /// corresponding unsigned 16-bit integers in \a __B, producing 2 intermediate
28 /// signed 16-bit results. Sum these 2 results with the corresponding
29 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
40 /// A 128-bit vector of [4 x int].
42 /// A 128-bit vector of [8 x short].
44 /// A 128-bit vector of [8 x unsigned short].
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H A Davx512bf16intrin.h1 /*===------------ avx512bf16intrin.h - AVX512_BF16 intrinsics --------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
27 __target__("avx512bf16,no-evex512")))
50 /// A 512-bit vector of [16 x float].
52 /// A 512-bit vector of [16 x float].
53 /// \returns A 512-bit vector of [32 x bfloat] whose lower 256 bits come from
68 /// A 512-bit vector of [16 x float].
70 /// A 512-bit vector of [16 x float].
72 /// A 512-bit vector of [32 x bfloat].
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H A Davxneconvertintrin.h1 /*===-------------- avxneconvertintrin.h - AVXNECONVERT --------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
28 /// Convert scalar BF16 (16-bit) floating-point element
30 /// single-precision (32-bit) floating-point, broadcast it to packed
31 /// single-precision (32-bit) floating-point elements, and store the results in
43 /// A pointer to a 16-bit memory location. The address of the memory
46 /// A 128-bit vector of [4 x float].
61 /// Convert scalar BF16 (16-bit) floating-point element
63 /// single-precision (32-bit) floating-point, broadcast it to packed
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H A Dmmintrin.h1 /*===---- mmintrin.h - MMX intrinsics -----
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H A Df16cintrin.h1 /*===---- f16cintrin.h - F16C intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
23 /* NOTE: Intel documents the 128-bit versions of these as being in emmintrin.h,
28 /// Converts a 16-bit half-precision float value into a 32-bit float
36 /// A 16-bit half-precision float value.
37 /// \returns The converted 32-bit float value.
46 /// Converts a 32-bit single-precision float value to a 16-bit
47 /// half-precision float value.
58 /// A 32-bit single-precision float value to be converted to a 16-bit
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H A Davx2intrin.h1 /*===---- avx2intrin.h - AVX2 intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
20 __target__("avx2,no-evex512"), __min_vector_width__(256)))
23 __target__("avx2,no-evex512"), __min_vector_width__(128)))
27 /// four unsigned 8-bit integers from the 256-bit integer vectors \a X and
31 /// vectors, and another eight using the upper half. These 16-bit values
32 /// are returned in the lower and upper halves of the 256-bit result,
38 /// difference, and sums these four values to form one 16-bit result. The
39 /// intrinsic computes 16 of these results with different sets of input
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/freebsd-src/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
40 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
41 #define MT_TX_FREE_PAIR BIT(31)
47 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
50 #define MT_TXD1_LONG_FORMAT BIT(31)
51 #define MT_TXD1_TGID BIT(30)
53 #define MT_TXD1_AMSDU BIT(23)
56 #define MT_TXD1_HDR_FORMAT GENMASK(17, 16)
58 #define MT_TXD1_ETH_802_3 BIT(15)
59 #define MT_TXD1_VTA BIT(10)
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H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
25 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
30 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
31 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
32 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
34 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
40 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
41 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
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H A Dmt76x02_regs.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
23 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
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/freebsd-src/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
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H A Dmac.h1 /* SPDX-License-Identifier: ISC */
9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
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/freebsd-src/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
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H A Dregs.h1 /* SPDX-License-Identifier: ISC */
35 #define MT_HW_INFO_BASE ((dev)->reg_map[MT_HW_BASE])
40 #define MT_TOP_3NSS BIT(24)
43 #define MT_TOP_OFF_RSV_FW_STATE GENMASK(18, 16)
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
49 #define MT_TOP_MISC2_FW_PWR_ON BIT(1)
59 #define MT_MCU_PCIE_REMAP_2 ((dev)->reg_map[MT_PCIE_REMAP_2])
62 #define MT_PCIE_REMAP_BASE_2 ((dev)->reg_map[MT_PCIE_REMAP_BASE2])
69 #define MT_HIF(ofs) ((dev)->reg_map[MT_HIF_BASE] + (ofs))
71 #define MT_HIF_LOGIC_RST_N BIT(4)
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/freebsd-src/sys/dev/qat/include/
H A Dicp_qat_hw.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
49 ICP_QAT_HW_AUTH_RESERVED_2 = 16,
83 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0),
84 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = BIT(1),
85 ICP_ACCEL_CAPABILITIES_CIPHER = BIT(2),
86 ICP_ACCEL_CAPABILITIES_AUTHENTICATION = BIT(3),
87 ICP_ACCEL_CAPABILITIES_RESERVED_1 = BIT(4),
88 ICP_ACCEL_CAPABILITIES_COMPRESSION = BIT(5),
89 ICP_ACCEL_CAPABILITIES_DEPRECATED = BIT(6),
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/freebsd-src/sys/dev/sfxge/common/
H A Defx_regs_pci.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
41 * PC_VEND_ID_REG(16bit):
49 #define PCRF_AZ_VEND_ID_WIDTH 16
52 * PC_DEV_ID_REG(16bit):
60 #define PCRF_AZ_DEV_ID_WIDTH 16
63 * PC_CMD_REG(16bit):
94 * PC_STAT_REG(16bit):
125 * PC_REV_ID_REG(8bit):
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/freebsd-src/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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/freebsd-src/contrib/wpa/src/crypto/
H A Dmilenage.c2 * 3GPP AKA - Milenage algorithm (3GPP TS 35.205, .206, .207, .208)
3 * Copyright (c) 2006-2007 <j@w1.fi>
10 * EAP-AKA to be tested properly with real USIM cards.
26 * milenage_f1 - Milenage f1 and f1* algorithms
27 * @opc: OPc = 128-bit value derived from OP and K
28 * @k: K = 128-bit subscriber key
29 * @_rand: RAND = 128-bit random challenge
30 * @sqn: SQN = 48-bit sequence number
31 * @amf: AMF = 16-bit authentication management field
32 * @mac_a: Buffer for MAC-A = 64-bit network authentication code, or %NULL
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/freebsd-src/sys/contrib/dev/rtw89/
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
27 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
40 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
48 if (rtwdev->chi in rtw89_get_data_mcs()
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H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(
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/freebsd-src/sys/dev/stge/
H A Dif_stgereg.h3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
46 * D-Link Systems PCI vendor ID
64 * D-Link Systems device ID
77 * Note that while DMA addresses are all in 64-bit fields, only
90 bus_write_4((_sc)->sc_res[0], (reg), (val))
92 bus_write_2((_sc)->sc_res[0], (reg), (val))
94 bus_write_1((_sc)->sc_res[0], (reg), (val))
97 bus_read_4((_sc)->sc_res[0], (reg))
99 bus_read_2((_sc)->sc_res[0], (reg))
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td1 //===-- RISCVSchedule.td - RISC-V Scheduling Definitions ---*- tablegen -*-
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/freebsd-src/sys/contrib/dev/rtw88/
H A Drtw8723d.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
20 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
/freebsd-src/sys/contrib/dev/athk/ath12k/
H A Ddp.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
152 #define DP_IDLE_SCATTER_BUFS_MAX 16
188 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; })
235 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */
238 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */
245 #define DP_REO_QREF_NUM GENMASK(31, 16)
255 #define DP_INVALID_BANK_ID -1
332 * - reo_cmd_list
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