Home
last modified time | relevance | path

Searched +full:0 +full:xba (Results 1 – 25 of 364) sorted by relevance

12345678910>>...15

/llvm-project/llvm/test/MC/Disassembler/Lanai/
H A Dv11.txt3 0x0a 0xc4 0x00 0x00
4 # CHECK: add %r17, 0x0, %r21
5 0x0a 0xc4 0x12 0x34
6 # CHECK: add %r17, 0x1234, %r21
7 0x0a 0xc5 0x12 0x34
8 # CHECK: add %r17, 0x12340000, %r21
9 0x0a 0xc6 0x00 0x00
10 # CHECK: add.f %r17, 0x0, %r21
11 0x0a 0xc6 0x12 0x34
12 # CHECK: add.f %r17, 0x1234, %r21
[all …]
/llvm-project/llvm/test/MC/Lanai/
H A Dv11.s3 add %r17, 0, %r21
4 ! CHECK: 0x0a,0xc4,0x00,0x00
5 add %r17, 0x00001234, %r21
6 ! CHECK: 0x0a,0xc4,0x12,0x34
7 add %r17, 0x12340000, %r21
8 ! CHECK: 0x0a,0xc5,0x12,0x34
9 add.f %r17, 0, %r21
10 ! CHECK: 0x0a,0xc6,0x00,0x00
11 add.f %r17, 0x00001234, %r21
12 ! CHECK: 0x0a,0xc6,0x12,0x34
[all …]
/llvm-project/llvm/test/MC/ARM/
H A Dthumb-neon-v8.s4 @ CHECK: vmaxnm.f32 d4, d5, d1 @ encoding: [0x05,0xff,0x11,0x4f]
6 @ CHECK: vmaxnm.f32 q2, q4, q6 @ encoding: [0x08,0xff,0x5c,0x4f]
8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x24,0xff,0x3e,0x5f]
10 @ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0x2a,0xff,0xd4,0x0f]
13 @ CHECK: vcvta.s32.f32 d4, d6 @ encoding: [0xbb,0xff,0x06,0x40]
15 @ CHECK: vcvta.u32.f32 d12, d10 @ encoding: [0xbb,0xff,0x8a,0xc0]
17 @ CHECK: vcvta.s32.f32 q4, q6 @ encoding: [0xbb,0xff,0x4c,0x80]
19 @ CHECK: vcvta.u32.f32 q4, q10 @ encoding: [0xbb,0xff,0xe4,0x80]
22 @ CHECK: vcvtm.s32.f32 d1, d30 @ encoding: [0xbb,0xff,0x2e,0x13]
24 @ CHECK: vcvtm.u32.f32 d12, d10 @ encoding: [0xbb,0xff,0x8a,0xc3]
[all …]
H A Dneon-v8.s4 @ CHECK: vmaxnm.f32 d4, d5, d1 @ encoding: [0x11,0x4f,0x05,0xf3]
6 @ CHECK: vmaxnm.f32 q2, q4, q6 @ encoding: [0x5c,0x4f,0x08,0xf3]
8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x3e,0x5f,0x24,0xf3]
10 @ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0xd4,0x0f,0x2a,0xf3]
13 @ CHECK: vcvta.s32.f32 d4, d6 @ encoding: [0x06,0x40,0xbb,0xf3]
15 @ CHECK: vcvta.u32.f32 d12, d10 @ encoding: [0x8a,0xc0,0xbb,0xf3]
17 @ CHECK: vcvta.s32.f32 q4, q6 @ encoding: [0x4c,0x80,0xbb,0xf3]
19 @ CHECK: vcvta.u32.f32 q4, q10 @ encoding: [0xe4,0x80,0xbb,0xf3]
22 @ CHECK: vcvtm.s32.f32 d1, d30 @ encoding: [0x2e,0x13,0xbb,0xf3]
24 @ CHECK: vcvtm.u32.f32 d12, d10 @ encoding: [0x8a,0xc3,0xbb,0xf3]
[all …]
H A Dneon-shuffle-encoding.s20 @ CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xf2]
21 @ CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xa0,0x05,0xf1,0xf2]
22 @ CHECK: vext.8 q8, q9, q8, #3 @ encoding: [0xe0,0x03,0xf2,0xf2]
23 @ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xe0,0x07,0xf2,0xf2]
24 @ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x06,0xf1,0xf2]
25 @ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xe0,0x0c,0xf2,0xf2]
26 @ CHECK: vext.64 q8, q9, q8, #1 @ encoding: [0xe0,0x08,0xf2,0xf2]
28 @ CHECK: vext.8 d17, d17, d16, #3 @ encoding: [0xa0,0x13,0xf1,0xf2]
29 @ CHECK: vext.8 d7, d7, d11, #5 @ encoding: [0x0b,0x75,0xb7,0xf2]
30 @ CHECK: vext.8 q3, q3, q8, #3 @ encoding: [0x60,0x63,0xb6,0xf2]
[all …]
H A Dmve-float.s7 # CHECK: vrintn.f16 q1, q0 @ encoding: [0xb6,0xff,0x40,0x24]
8 # CHECK-NOFP-NOT: vrintn.f16 q1, q0 @ encoding: [0xb6,0xff,0x40,0x24]
11 # CHECK: vrintn.f32 q0, q4 @ encoding: [0xba,0xff,0x48,0x04]
12 # CHECK-NOFP-NOT: vrintn.f32 q0, q4 @ encoding: [0xba,0xff,0x48,0x04]
15 # CHECK: vrinta.f16 q0, q1 @ encoding: [0xb6,0xff,0x42,0x05]
16 # CHECK-NOFP-NOT: vrinta.f16 q0, q1 @ encoding: [0xb6,0xff,0x42,0x05]
19 # CHECK: vrinta.f32 q1, q3 @ encoding: [0xba,0xff,0x46,0x25]
20 # CHECK-NOFP-NOT: vrinta.f32 q1, q3 @ encoding: [0xba,0xff,0x46,0x25]
23 # CHECK: vrintm.f16 q0, q5 @ encoding: [0xb6,0xff,0xca,0x06]
24 # CHECK-NOFP-NOT: vrintm.f16 q0, q5 @ encoding: [0xb6,0xff,0xca,0x06]
[all …]
H A Dthumb.s5 @ CHECK: cmp r1, r2 @ encoding: [0x91,0x42]
8 @ CHECK: pop {r1, r2, r4} @ encoding: [0x16,0xbc]
11 @ CHECK: trap @ encoding: [0xfe,0xde]
15 @ CHECK: blx r9 @ encoding: [0xc8,0x47]
16 @ CHECK: blx r10 @ encoding: [0xd0,0x47]
21 @ CHECK: rev r2, r3 @ encoding: [0x1a,0xba]
22 @ CHECK: rev16 r3, r4 @ encoding: [0x63,0xba]
23 @ CHECK: revsh r5, r6 @ encoding: [0xf5,0xba]
27 @ CHECK: sxtb r2, r3 @ encoding: [0x5a,0xb2]
28 @ CHECK: sxth r2, r3 @ encoding: [0x1a,0xb2]
[all …]
/llvm-project/llvm/test/MC/Disassembler/ARM/
H A Dneon-v8.txt3 0x11 0x4f 0x05 0xf3
5 0x5c 0x4f 0x08 0xf3
7 0x3e 0x5f 0x24 0xf3
9 0xd4 0x0f 0x2a 0xf3
12 0x06 0x40 0xbb 0xf3
14 0x8a 0xc0 0xbb 0xf3
16 0x4c 0x80 0xbb 0xf3
18 0xe4 0x80 0xbb 0xf3
21 0x2e 0x13 0xbb 0xf3
23 0x8a 0xc3 0xbb 0xf3
[all …]
H A Dthumb-neon-v8.txt3 0x5 0xff 0x11 0x4f
5 0x08 0xff 0x5c 0x4f
7 0x24 0xff 0x3e 0x5f
9 0x2a 0xff 0xd4 0x0f
12 0xbb 0xff 0x06 0x40
14 0xbb 0xff 0x8a 0xc0
16 0xbb 0xff 0x4c 0x80
18 0xbb 0xff 0xe4 0x80
21 0xbb 0xff 0x2e 0x13
23 0xbb 0xff 0x8a 0xc3
[all …]
H A Dmve-float.txt5 # CHECK: vrintn.f16 q1, q0 @ encoding: [0xb6,0xff,0x40,0x24]
7 [0xb6,0xff,0x40,0x24]
9 # CHECK: vrintn.f32 q0, q4 @ encoding: [0xba,0xff,0x48,0x04]
11 [0xba,0xff,0x48,0x04]
13 # CHECK: vrinta.f16 q0, q1 @ encoding: [0xb6,0xff,0x42,0x05]
15 [0xb6,0xff,0x42,0x05]
17 # CHECK: vrinta.f32 q1, q3 @ encoding: [0xba,0xff,0x46,0x25]
19 [0xba,0xff,0x46,0x25]
21 # CHECK: vrintm.f16 q0, q5 @ encoding: [0xb6,0xff,0xca,0x06]
23 [0xb6,0xff,0xca,0x06]
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.amdgcn.s.setreg.ll12 ; Offset: fp_round = 0, fp_denorm = 4, dx10_clamp = 8, ieee_mode = 9
18 ; GFX6: ; %bb.0:
19 …NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xba,0x03,0x00…
22 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
25 ; GFX789: ; %bb.0:
26 …NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x00,0xba,0x03,0x00…
29 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
32 ; GFX10: ; %bb.0:
33 …NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xba,0x03,0x00…
36 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.s.setreg.ll12 ; Offset: fp_round = 0, fp_denorm = 4, dx10_clamp = 8, ieee_mode = 9
18 ; GFX6: ; %bb.0:
19 …NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xba,0x03,0x00…
22 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
25 ; GFX789: ; %bb.0:
26 …NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x00,0xba,0x03,0x00…
29 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
32 ; GFX10: ; %bb.0:
33 …NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xba,0x03,0x00…
36 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
[all …]
/llvm-project/llvm/test/MC/X86/
H A Dx86-32-coverage.s5 // CHECK: encoding: [0xd9,0x07]
9 // CHECK: encoding: [0xdf,0x07]
13 // CHECK: encoding: [0xc6,0x84,0xcb,0xef,0xbe,0xa
[all...]
H A DI386-64.s4 // CHECK: encoding: [0x66,0x45,0x0f,0xbc,0xed]
8 // CHECK: encoding: [0x66,0x45,0x0f,0xbd,0xed]
12 // CHECK: encoding: [0x45,0x0f,0xbc,0xed]
16 // CHECK: encoding: [0x45,0x0f,0xbd,0xed]
20 // CHECK: encoding: [0x4d,0x0f,0xbc,0xed]
24 // CHECK: encoding: [0x4d,0x0f,0xbd,0xed]
28 // CHECK: btcw $0, %r13w
29 // CHECK: encoding: [0x66,0x41,0x0f,0xba,0xfd,0x00]
30 btcw $0, %r13w
33 // CHECK: encoding: [0x66,0x41,0x0f,0xba,0xfd,0xff]
[all …]
H A DI386-32.s4 // CHECK: encoding: [0x66,0x0f,0xbc,0xc0]
8 // CHECK: encoding: [0x66,0x0f,0xbd,0xc0]
12 // CHECK: encoding: [0x0f,0xbc,0xc0]
16 // CHECK: encoding: [0x0f,0xbd,0xc0]
19 // CHECK: btcw $0, %ax
20 // CHECK: encoding: [0x66,0x0f,0xba,0xf8,0x00]
21 btcw $0, %ax
24 // CHECK: encoding: [0x66,0x0f,0xba,0xf8,0xff]
28 // CHECK: encoding: [0x66,0x0f,0xba,0xf8,0xff]
32 // CHECK: encoding: [0x66,0x0f,0xbb,0xc0]
[all …]
/llvm-project/llvm/test/MC/RISCV/
H A Dlarge-instructions.s5 .byte 0x1f, 0x01, 0x23, 0x45, 0x67, 0x89
8 .byte 0x3f, 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd
11 .byte 0x7f, 0x00, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0xfe
14 .byte 0x7f, 0x10, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0xfe, 0xdc, 0xba
17 .byte 0x7f, 0x20, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0xfe, 0xdc, 0xba, 0x98, 0x76
20 .byte 0x7f, 0x30, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32
23 .byte 0x7f, 0x40, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x3…
26 .byte 0x7f, 0x50, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x3…
29 .byte 0x7f, 0x60, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x3…
H A Drv32zcmp-valid.s8 # CHECK-ASM: encoding: [0xa2,0xac]
12 # CHECK-ASM: encoding: [0xe2,0xac]
16 # CHECK-ASM: encoding: [0x62,0xac]
20 # CHECK-ASM: encoding: [0x42,0xbe]
24 # CHECK-ASM: encoding: [0x42,0xb
[all...]
H A Drv64zcmp-valid.s8 # CHECK-ASM: encoding: [0xa2,0xac]
12 # CHECK-ASM: encoding: [0xe2,0xac]
16 # CHECK-ASM: encoding: [0x42,0xbe]
20 # CHECK-ASM: encoding: [0x46,0xbe]
24 # CHECK-ASM: encoding: [0x5e,0xb
[all...]
H A Drv64e-zcmp-valid.s8 # CHECK-ASM: encoding: [0xa2,0xac]
12 # CHECK-ASM: encoding: [0xe2,0xac]
16 # CHECK-ASM: encoding: [0x42,0xbe]
20 # CHECK-ASM: encoding: [0x46,0xbe]
24 # CHECK-ASM: encoding: [0x5e,0xb
[all...]
/llvm-project/llvm/test/MC/VE/
H A DVCPX.s7 # CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x94,0x20,0xba]
11 # CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xba]
15 # CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x20,0xba]
19 # CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x3f,0x2b,0xba]
23 # CHECK-ENCODING: encoding: [0x00,0x16,0x17,0x0b,0x00,0x00,0x0b,0xba]
/llvm-project/llvm/unittests/Support/
H A DDJBTest.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
37 {{/*U+139*/ "\xc4\xb9"}, {/*U+13a*/ "\xc4\xba"}}, in TEST()
41 {{/*U+1ea6*/ "\xe1\xba\xa6"}, {/*U+1ea7*/ "\xe1\xba\xa7"}}, in TEST()
87 djbHash("\xc4\xb0\xc4\xb1\xc3\x80\xc3\xa0\xc4\x80\xc4\x81\xc4\xb9\xc4\xba" in TEST()
88 "\xd0\x95\xd0\xb5\xe1\xba\xa6\xe1\xba\xa7\xe2\x84\xaa\x6b\xe2\xb0" in TEST()
94 "\xc4\xb0\xc4\xb1\xc3\x80\xc3\xa0\xc4\x80\xc4\x81\xc4\xb9\xc4\xba" in TEST()
95 "\xd0\x95\xd0\xb5\xe1\xba\xa6\xe1\xba\xa7\xe2\x84\xaa\x6b\xe2\xb0" in TEST()
/llvm-project/llvm/test/CodeGen/X86/
H A Dsse42-intrinsics-x86.ll13 ; SSE: ## %bb.0:
14 ; SSE-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
15 ; SSE-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
16 ; SSE-NEXT: pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
17 ; SSE-NEXT: movl %ecx, %eax ## encoding: [0x89,0xc8]
18 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
21 ; AVX: ## %bb.0:
22 ; AVX-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
23 ; AVX-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
24 ; AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
[all …]
/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx12_dasm_sopk.txt4 # GFX12: s_addk_co_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0xff,0xb7]
5 0x34,0x12,0xff,0xb7
7 # GFX12: s_addk_co_i32 exec_lo, 0x123
[all...]
/llvm-project/llvm/test/MC/AArch64/SME2/
H A Dsrshl.s17 // CHECK-ENCODING: [0x20,0xa2,0x60,0xc1]
23 // CHECK-ENCODING: [0x34,0xa2,0x65,0xc1]
29 // CHECK-ENCODING: [0x36,0xa2,0x68,0xc1]
35 // CHECK-ENCODING: [0x3e,0xa2,0x6f,0xc1]
42 // CHECK-ENCODING: [0x20,0xb2,0x60,0xc1]
48 // CHECK-ENCODING: [0x34,0xb2,0x74,0xc1]
54 // CHECK-ENCODING: [0x36,0xb2,0x68,0xc1]
60 // CHECK-ENCODING: [0x3e,0xb2,0x7e,0xc1]
67 // CHECK-ENCODING: [0x20,0xa2,0xa0,0xc1]
73 // CHECK-ENCODING: [0x34,0xa2,0xa5,0xc1]
[all …]
H A Durshl.s17 // CHECK-ENCODING: [0x21,0xa2,0x60,0xc1]
23 // CHECK-ENCODING: [0x35,0xa2,0x65,0xc1]
29 // CHECK-ENCODING: [0x37,0xa2,0x68,0xc1]
35 // CHECK-ENCODING: [0x3f,0xa2,0x6f,0xc1]
42 // CHECK-ENCODING: [0x21,0xb2,0x60,0xc1]
48 // CHECK-ENCODING: [0x35,0xb2,0x74,0xc1]
54 // CHECK-ENCODING: [0x37,0xb2,0x68,0xc1]
60 // CHECK-ENCODING: [0x3f,0xb2,0x7e,0xc1]
67 // CHECK-ENCODING: [0x21,0xa2,0xa0,0xc1]
73 // CHECK-ENCODING: [0x35,0xa2,0xa5,0xc1]
[all …]

12345678910>>...15