Lines Matching +full:0 +full:xba

12 ; Offset: fp_round = 0, fp_denorm = 4, dx10_clamp = 8, ieee_mode = 9
18 ; GFX6:       ; %bb.0:
19 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xba,0x03,0x00…
22 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
25 ; GFX789:       ; %bb.0:
26 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x00,0xba,0x03,0x00…
29 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
32 ; GFX10:       ; %bb.0:
33 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xba,0x03,0x00…
36 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
39 ; GFX11:       ; %bb.0:
40 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xb9,0x03,0x00…
43 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
52 ; GFX6:       ; %bb.0:
53 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xba,0x03,0x00,0x00,0x00]
56 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
59 ; GFX789:       ; %bb.0:
60 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x00,0xba,0x03,0x00,0x00,0x00]
63 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
66 ; GFX10:       ; %bb.0:
67 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xba,0x03,0x00,0x00,0x00]
70 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
73 ; GFX11:       ; %bb.0:
74 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xb9,0x03,0x00,0x00,0x00]
77 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
86 ; GFX6:       ; %bb.0:
87 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x80,0xba,0x07,0x00,0x00,0x00]
90 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
93 ; GFX789:       ; %bb.0:
94 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x00,0xba,0x07,0x00,0x00,0x00]
97 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
100 ; GFX10:       ; %bb.0:
101 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x80,0xba,0x07,0x00,0x00,0x00]
104 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
107 ; GFX11:       ; %bb.0:
108 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x80,0xb9,0x07,0x00,0x00,0x00]
111 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
120 ; GFX6:       ; %bb.0:
121 ; GFX6-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x80,0xb9]
124 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
127 ; GFX789:       ; %bb.0:
128 ; GFX789-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x00,0xb9]
131 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
134 ; GFX10:       ; %bb.0:
135 ; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x80,0xb9]
138 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
141 ; GFX11:       ; %bb.0:
142 ; GFX11-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x00,0xb9]
145 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
153 ; GFX6:       ; %bb.0:
154 …T:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x80,0xba,0x00,0x00,0x…
157 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
160 ; GFX789:       ; %bb.0:
161 …T:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x00,0xba,0x00,0x00,0x…
164 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
167 ; GFX10:       ; %bb.0:
168 …T:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x80,0xba,0x00,0x00,0x…
171 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
174 ; GFX11:       ; %bb.0:
175 …T:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x80,0xb9,0x00,0x00,0x…
178 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
179   call void @llvm.amdgcn.s.setreg(i32 577, i32 0)
186 ; GFX6:       ; %bb.0:
187 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x80,0xba,0x01,0x00,0x00,0x00]
190 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
193 ; GFX789:       ; %bb.0:
194 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x00,0xba,0x01,0x00,0x00,0x00]
197 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
200 ; GFX10:       ; %bb.0:
201 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x80,0xba,0x01,0x00,0x00,0x00]
204 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
207 ; GFX11:       ; %bb.0:
208 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x80,0xb9,0x01,0x00,0x00,0x00]
211 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
219 ; GFX6:       ; %bb.0:
220 …T:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x80,0xba,0x00,0x00,0x…
223 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
226 ; GFX789:       ; %bb.0:
227 …T:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x00,0xba,0x00,0x00,0x…
230 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
233 ; GFX10:       ; %bb.0:
234 …T:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x80,0xba,0x00,0x00,0x…
237 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
240 ; GFX11:       ; %bb.0:
241 …T:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x80,0xb9,0x00,0x00,0x…
244 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
245   call void @llvm.amdgcn.s.setreg(i32 513, i32 0)
252 ; GFX6:       ; %bb.0:
253 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x80,0xba,0x01,0x00,0x00,0x00]
256 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
259 ; GFX789:       ; %bb.0:
260 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x00,0xba,0x01,0x00,0x00,0x00]
263 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
266 ; GFX10:       ; %bb.0:
267 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x80,0xba,0x01,0x00,0x00,0x00]
270 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
273 ; GFX11:       ; %bb.0:
274 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x80,0xb9,0x01,0x00,0x00,0x00]
277 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
286 ; GFX6:       ; %bb.0:
287 ; GFX6-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x80,0xb9]
290 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
293 ; GFX789:       ; %bb.0:
294 ; GFX789-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x00,0xb9]
297 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
300 ; GFX10:       ; %bb.0:
301 ; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x80,0xb9]
304 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
307 ; GFX11:       ; %bb.0:
308 ; GFX11-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x00,0xb9]
311 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
320 ; GFX6:       ; %bb.0:
321 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x80,0xba,0x06,0x00…
324 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
327 ; GFX789:       ; %bb.0:
328 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x00,0xba,0x06,0x00…
331 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
334 ; GFX10:       ; %bb.0:
335 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x80,0xba,0x06,0x00…
338 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
341 ; GFX11:       ; %bb.0:
342 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x80,0xb9,0x06,0x00…
345 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
354 ; GFX6:       ; %bb.0:
355 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x80,0xba,0x06,0x00,0x00,0x00]
358 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
361 ; GFX789:       ; %bb.0:
362 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x00,0xba,0x06,0x00,0x00,0x00]
365 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
368 ; GFX10:       ; %bb.0:
369 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x80,0xba,0x06,0x00,0x00,0x00]
372 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
375 ; GFX11:       ; %bb.0:
376 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x80,0xb9,0x06,0x00,0x00,0x00]
379 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
387 ; GFX6:       ; %bb.0:
388 ; GFX6-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x80,0xb9]
391 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
394 ; GFX789:       ; %bb.0:
395 ; GFX789-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x00,0xb9]
398 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
401 ; GFX10:       ; %bb.0:
402 ; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x80,0xb9]
405 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
408 ; GFX11:       ; %bb.0:
409 ; GFX11-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x00,0xb9]
412 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
420 ; GFX6:       ; %bb.0:
421 ; GFX6-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x80,0xb9]
424 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
427 ; GFX789:       ; %bb.0:
428 ; GFX789-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x00,0xb9]
431 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
434 ; GFX10:       ; %bb.0:
435 ; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x80,0xb9]
438 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
441 ; GFX11:       ; %bb.0:
442 ; GFX11-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x00,0xb9]
445 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
453 ; GFX6:       ; %bb.0:
454 ; GFX6-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x80,0xb9]
457 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
460 ; GFX789:       ; %bb.0:
461 ; GFX789-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x00,0xb9]
464 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
467 ; GFX10:       ; %bb.0:
468 ; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x80,0xb9]
471 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
474 ; GFX11:       ; %bb.0:
475 ; GFX11-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x00,0xb9]
478 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
486 ; GFX6:       ; %bb.0:
487 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 0 ; encoding: [0x01,0x18,0x80,0xba,0x00,0x00…
490 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
493 ; GFX789:       ; %bb.0:
494 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 0 ; encoding: [0x01,0x18,0x00,0xba,0x00,0x00…
497 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
500 ; GFX10:       ; %bb.0:
501 ; GFX10-NEXT:    s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]
504 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
507 ; GFX11:       ; %bb.0:
508 ; GFX11-NEXT:    s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf]
511 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
512   call void @llvm.amdgcn.s.setreg(i32 6145, i32 0)
519 ; GFX6:       ; %bb.0:
520 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 1 ; encoding: [0x01,0x18,0x80,0xba,0x01,0x00…
523 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
526 ; GFX789:       ; %bb.0:
527 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 1 ; encoding: [0x01,0x18,0x00,0xba,0x01,0x00…
530 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
533 ; GFX10:       ; %bb.0:
534 ; GFX10-NEXT:    s_round_mode 0x1 ; encoding: [0x01,0x00,0xa4,0xbf]
537 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
540 ; GFX11:       ; %bb.0:
541 ; GFX11-NEXT:    s_round_mode 0x1 ; encoding: [0x01,0x00,0x91,0xbf]
544 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
552 ; GFX6:       ; %bb.0:
553 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 2 ; encoding: [0x01,0x18,0x80,0xba,0x02,0x00…
556 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
559 ; GFX789:       ; %bb.0:
560 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 2 ; encoding: [0x01,0x18,0x00,0xba,0x02,0x00…
563 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
566 ; GFX10:       ; %bb.0:
567 ; GFX10-NEXT:    s_round_mode 0x2 ; encoding: [0x02,0x00,0xa4,0xbf]
570 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
573 ; GFX11:       ; %bb.0:
574 ; GFX11-NEXT:    s_round_mode 0x2 ; encoding: [0x02,0x00,0x91,0xbf]
577 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
585 ; GFX6:       ; %bb.0:
586 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 4 ; encoding: [0x01,0x18,0x80,0xba,0x04,0x00…
589 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
592 ; GFX789:       ; %bb.0:
593 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 4 ; encoding: [0x01,0x18,0x00,0xba,0x04,0x00…
596 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
599 ; GFX10:       ; %bb.0:
600 ; GFX10-NEXT:    s_round_mode 0x4 ; encoding: [0x04,0x00,0xa4,0xbf]
603 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
606 ; GFX11:       ; %bb.0:
607 ; GFX11-NEXT:    s_round_mode 0x4 ; encoding: [0x04,0x00,0x91,0xbf]
610 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
618 ; GFX6:       ; %bb.0:
619 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 8 ; encoding: [0x01,0x18,0x80,0xba,0x08,0x00…
622 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
625 ; GFX789:       ; %bb.0:
626 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 8 ; encoding: [0x01,0x18,0x00,0xba,0x08,0x00…
629 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
632 ; GFX10:       ; %bb.0:
633 ; GFX10-NEXT:    s_round_mode 0x8 ; encoding: [0x08,0x00,0xa4,0xbf]
636 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
639 ; GFX11:       ; %bb.0:
640 ; GFX11-NEXT:    s_round_mode 0x8 ; encoding: [0x08,0x00,0x91,0xbf]
643 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
651 ; GFX6:       ; %bb.0:
652 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 15 ; encoding: [0x01,0x18,0x80,0xba,0x0f,0x0…
655 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
658 ; GFX789:       ; %bb.0:
659 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 15 ; encoding: [0x01,0x18,0x00,0xba,0x0f,0x0…
662 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
665 ; GFX10:       ; %bb.0:
666 ; GFX10-NEXT:    s_round_mode 0xf ; encoding: [0x0f,0x00,0xa4,0xbf]
669 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
672 ; GFX11:       ; %bb.0:
673 ; GFX11-NEXT:    s_round_mode 0xf ; encoding: [0x0f,0x00,0x91,0xbf]
676 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
685 ; GFX6:       ; %bb.0:
686 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 42 ; encoding: [0x01,0x18,0x80,0xba,0x2a,0x0…
689 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
692 ; GFX789:       ; %bb.0:
693 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 42 ; encoding: [0x01,0x18,0x00,0xba,0x2a,0x0…
696 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
699 ; GFX10:       ; %bb.0:
700 ; GFX10-NEXT:    s_round_mode 0xa ; encoding: [0x0a,0x00,0xa4,0xbf]
703 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
706 ; GFX11:       ; %bb.0:
707 ; GFX11-NEXT:    s_round_mode 0xa ; encoding: [0x0a,0x00,0x91,0xbf]
710 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
718 ; GFX6:       ; %bb.0:
719 …T:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 0 ; encoding: [0x01,0x19,0x80,0xba,0x00,0x00,0x…
722 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
725 ; GFX789:       ; %bb.0:
726 …T:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 0 ; encoding: [0x01,0x19,0x00,0xba,0x00,0x00,0x…
729 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
732 ; GFX10:       ; %bb.0:
733 ; GFX10-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
736 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
739 ; GFX11:       ; %bb.0:
740 ; GFX11-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]
743 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
744   call void @llvm.amdgcn.s.setreg(i32 6401, i32 0)
751 ; GFX6:       ; %bb.0:
752 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 1 ; encoding: [0x01,0x19,0x80,0xba,0x01,0x00,0x00,0x00]
755 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
758 ; GFX789:       ; %bb.0:
759 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 1 ; encoding: [0x01,0x19,0x00,0xba,0x01,0x00,0x00,0x00]
762 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
765 ; GFX10:       ; %bb.0:
766 ; GFX10-NEXT:    s_denorm_mode 1 ; encoding: [0x01,0x00,0xa5,0xbf]
769 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
772 ; GFX11:       ; %bb.0:
773 ; GFX11-NEXT:    s_denorm_mode 1 ; encoding: [0x01,0x00,0x92,0xbf]
776 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
785 ; GFX6:       ; %bb.0:
786 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 2 ; encoding: [0x01,0x19,0x80,0xba,0x02,0x00,0x00,0x00]
789 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
792 ; GFX789:       ; %bb.0:
793 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 2 ; encoding: [0x01,0x19,0x00,0xba,0x02,0x00,0x00,0x00]
796 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
799 ; GFX10:       ; %bb.0:
800 ; GFX10-NEXT:    s_denorm_mode 2 ; encoding: [0x02,0x00,0xa5,0xbf]
803 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
806 ; GFX11:       ; %bb.0:
807 ; GFX11-NEXT:    s_denorm_mode 2 ; encoding: [0x02,0x00,0x92,0xbf]
810 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
818 ; GFX6:       ; %bb.0:
819 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 4 ; encoding: [0x01,0x19,0x80,0xba,0x04,0x00,0x00,0x00]
822 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
825 ; GFX789:       ; %bb.0:
826 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 4 ; encoding: [0x01,0x19,0x00,0xba,0x04,0x00,0x00,0x00]
829 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
832 ; GFX10:       ; %bb.0:
833 ; GFX10-NEXT:    s_denorm_mode 4 ; encoding: [0x04,0x00,0xa5,0xbf]
836 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
839 ; GFX11:       ; %bb.0:
840 ; GFX11-NEXT:    s_denorm_mode 4 ; encoding: [0x04,0x00,0x92,0xbf]
843 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
851 ; GFX6:       ; %bb.0:
852 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 8 ; encoding: [0x01,0x19,0x80,0xba,0x08,0x00,0x00,0x00]
855 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
858 ; GFX789:       ; %bb.0:
859 …_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 8 ; encoding: [0x01,0x19,0x00,0xba,0x08,0x00,0x00,0x00]
862 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
865 ; GFX10:       ; %bb.0:
866 ; GFX10-NEXT:    s_denorm_mode 8 ; encoding: [0x08,0x00,0xa5,0xbf]
869 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
872 ; GFX11:       ; %bb.0:
873 ; GFX11-NEXT:    s_denorm_mode 8 ; encoding: [0x08,0x00,0x92,0xbf]
876 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
884 ; GFX6:       ; %bb.0:
885 …setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 15 ; encoding: [0x01,0x19,0x80,0xba,0x0f,0x00,0x00,0x00]
888 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
891 ; GFX789:       ; %bb.0:
892 …setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 15 ; encoding: [0x01,0x19,0x00,0xba,0x0f,0x00,0x00,0x00]
895 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
898 ; GFX10:       ; %bb.0:
899 ; GFX10-NEXT:    s_denorm_mode 15 ; encoding: [0x0f,0x00,0xa5,0xbf]
902 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
905 ; GFX11:       ; %bb.0:
906 ; GFX11-NEXT:    s_denorm_mode 15 ; encoding: [0x0f,0x00,0x92,0xbf]
909 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
917 ; GFX6:       ; %bb.0:
918 …setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 42 ; encoding: [0x01,0x19,0x80,0xba,0x2a,0x00,0x00,0x00]
921 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
924 ; GFX789:       ; %bb.0:
925 …setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 42 ; encoding: [0x01,0x19,0x00,0xba,0x2a,0x00,0x00,0x00]
928 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
931 ; GFX10:       ; %bb.0:
932 ; GFX10-NEXT:    s_denorm_mode 10 ; encoding: [0x0a,0x00,0xa5,0xbf]
935 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
938 ; GFX11:       ; %bb.0:
939 ; GFX11-NEXT:    s_denorm_mode 10 ; encoding: [0x0a,0x00,0x92,0xbf]
942 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
951 ; GFX6:       ; %bb.0:
952 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0 ; encoding: [0x01,0x38,0x80,0xba,0x00,0x00…
955 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
958 ; GFX789:       ; %bb.0:
959 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0 ; encoding: [0x01,0x38,0x00,0xba,0x00,0x00…
962 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
965 ; GFX10:       ; %bb.0:
966 ; GFX10-NEXT:    s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]
969 ; GFX10-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
970 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
973 ; GFX11:       ; %bb.0:
974 ; GFX11-NEXT:    s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf]
977 ; GFX11-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]
978 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
979   call void @llvm.amdgcn.s.setreg(i32 14337, i32 0)
986 ; GFX6:       ; %bb.0:
987 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 1 ; encoding: [0x01,0x38,0x80,0xba,0x01,0x00…
990 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
993 ; GFX789:       ; %bb.0:
994 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 1 ; encoding: [0x01,0x38,0x00,0xba,0x01,0x00…
997 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1000 ; GFX10:       ; %bb.0:
1001 ; GFX10-NEXT:    s_round_mode 0x1 ; encoding: [0x01,0x00,0xa4,0xbf]
1004 ; GFX10-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
1005 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1008 ; GFX11:       ; %bb.0:
1009 ; GFX11-NEXT:    s_round_mode 0x1 ; encoding: [0x01,0x00,0x91,0xbf]
1012 ; GFX11-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]
1013 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1021 ; GFX6:       ; %bb.0:
1022 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 2 ; encoding: [0x01,0x38,0x80,0xba,0x02,0x00…
1025 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1028 ; GFX789:       ; %bb.0:
1029 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 2 ; encoding: [0x01,0x38,0x00,0xba,0x02,0x00…
1032 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1035 ; GFX10:       ; %bb.0:
1036 ; GFX10-NEXT:    s_round_mode 0x2 ; encoding: [0x02,0x00,0xa4,0xbf]
1039 ; GFX10-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
1040 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1043 ; GFX11:       ; %bb.0:
1044 ; GFX11-NEXT:    s_round_mode 0x2 ; encoding: [0x02,0x00,0x91,0xbf]
1047 ; GFX11-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]
1048 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1056 ; GFX6:       ; %bb.0:
1057 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 4 ; encoding: [0x01,0x38,0x80,0xba,0x04,0x00…
1060 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1063 ; GFX789:       ; %bb.0:
1064 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 4 ; encoding: [0x01,0x38,0x00,0xba,0x04,0x00…
1067 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1070 ; GFX10:       ; %bb.0:
1071 ; GFX10-NEXT:    s_round_mode 0x4 ; encoding: [0x04,0x00,0xa4,0xbf]
1074 ; GFX10-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
1075 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1078 ; GFX11:       ; %bb.0:
1079 ; GFX11-NEXT:    s_round_mode 0x4 ; encoding: [0x04,0x00,0x91,0xbf]
1082 ; GFX11-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]
1083 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1091 ; GFX6:       ; %bb.0:
1092 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 8 ; encoding: [0x01,0x38,0x80,0xba,0x08,0x00…
1095 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1098 ; GFX789:       ; %bb.0:
1099 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 8 ; encoding: [0x01,0x38,0x00,0xba,0x08,0x00…
1102 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1105 ; GFX10:       ; %bb.0:
1106 ; GFX10-NEXT:    s_round_mode 0x8 ; encoding: [0x08,0x00,0xa4,0xbf]
1109 ; GFX10-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
1110 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1113 ; GFX11:       ; %bb.0:
1114 ; GFX11-NEXT:    s_round_mode 0x8 ; encoding: [0x08,0x00,0x91,0xbf]
1117 ; GFX11-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]
1118 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1126 ; GFX6:       ; %bb.0:
1127 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 16 ; encoding: [0x01,0x38,0x80,0xba,0x10,0x0…
1130 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1133 ; GFX789:       ; %bb.0:
1134 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 16 ; encoding: [0x01,0x38,0x00,0xba,0x10,0x0…
1137 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1140 ; GFX10:       ; %bb.0:
1141 ; GFX10-NEXT:    s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]
1144 ; GFX10-NEXT:    s_denorm_mode 1 ; encoding: [0x01,0x00,0xa5,0xbf]
1145 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1148 ; GFX11:       ; %bb.0:
1149 ; GFX11-NEXT:    s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf]
1152 ; GFX11-NEXT:    s_denorm_mode 1 ; encoding: [0x01,0x00,0x92,0xbf]
1153 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1161 ; GFX6:       ; %bb.0:
1162 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 32 ; encoding: [0x01,0x38,0x80,0xba,0x20,0x0…
1165 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1168 ; GFX789:       ; %bb.0:
1169 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 32 ; encoding: [0x01,0x38,0x00,0xba,0x20,0x0…
1172 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1175 ; GFX10:       ; %bb.0:
1176 ; GFX10-NEXT:    s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]
1179 ; GFX10-NEXT:    s_denorm_mode 2 ; encoding: [0x02,0x00,0xa5,0xbf]
1180 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1183 ; GFX11:       ; %bb.0:
1184 ; GFX11-NEXT:    s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf]
1187 ; GFX11-NEXT:    s_denorm_mode 2 ; encoding: [0x02,0x00,0x92,0xbf]
1188 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1196 ; GFX6:       ; %bb.0:
1197 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 64 ; encoding: [0x01,0x38,0x80,0xba,0x40,0x0…
1200 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1203 ; GFX789:       ; %bb.0:
1204 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 64 ; encoding: [0x01,0x38,0x00,0xba,0x40,0x0…
1207 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1210 ; GFX10:       ; %bb.0:
1211 ; GFX10-NEXT:    s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]
1214 ; GFX10-NEXT:    s_denorm_mode 4 ; encoding: [0x04,0x00,0xa5,0xbf]
1215 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1218 ; GFX11:       ; %bb.0:
1219 ; GFX11-NEXT:    s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf]
1222 ; GFX11-NEXT:    s_denorm_mode 4 ; encoding: [0x04,0x00,0x92,0xbf]
1223 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1231 ; GFX6:       ; %bb.0:
1232 …EXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x80 ; encoding: [0x01,0x38,0x80,0xba,0x80,0x…
1235 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1238 ; GFX789:       ; %bb.0:
1239 …EXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x80 ; encoding: [0x01,0x38,0x00,0xba,0x80,0x…
1242 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1245 ; GFX10:       ; %bb.0:
1246 ; GFX10-NEXT:    s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]
1249 ; GFX10-NEXT:    s_denorm_mode 8 ; encoding: [0x08,0x00,0xa5,0xbf]
1250 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1253 ; GFX11:       ; %bb.0:
1254 ; GFX11-NEXT:    s_round_mode 0x0 ; encoding: [0x00,0x00,0x91,0xbf]
1257 ; GFX11-NEXT:    s_denorm_mode 8 ; encoding: [0x08,0x00,0x92,0xbf]
1258 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1266 ; GFX6:       ; %bb.0:
1267 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 15 ; encoding: [0x01,0x38,0x80,0xba,0x0f,0x0…
1270 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1273 ; GFX789:       ; %bb.0:
1274 …NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 15 ; encoding: [0x01,0x38,0x00,0xba,0x0f,0x0…
1277 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1280 ; GFX10:       ; %bb.0:
1281 ; GFX10-NEXT:    s_round_mode 0xf ; encoding: [0x0f,0x00,0xa4,0xbf]
1284 ; GFX10-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
1285 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1288 ; GFX11:       ; %bb.0:
1289 ; GFX11-NEXT:    s_round_mode 0xf ; encoding: [0x0f,0x00,0x91,0xbf]
1292 ; GFX11-NEXT:    s_denorm_mode 0 ; encoding: [0x00,0x00,0x92,0xbf]
1293 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1301 ; GFX6:       ; %bb.0:
1302 …EXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0xff ; encoding: [0x01,0x38,0x80,0xba,0xff,0x…
1305 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1308 ; GFX789:       ; %bb.0:
1309 …EXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0xff ; encoding: [0x01,0x38,0x00,0xba,0xff,0x…
1312 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1315 ; GFX10:       ; %bb.0:
1316 ; GFX10-NEXT:    s_round_mode 0xf ; encoding: [0x0f,0x00,0xa4,0xbf]
1319 ; GFX10-NEXT:    s_denorm_mode 15 ; encoding: [0x0f,0x00,0xa5,0xbf]
1320 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1323 ; GFX11:       ; %bb.0:
1324 ; GFX11-NEXT:    s_round_mode 0xf ; encoding: [0x0f,0x00,0x91,0xbf]
1327 ; GFX11-NEXT:    s_denorm_mode 15 ; encoding: [0x0f,0x00,0x92,0xbf]
1328 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1337 ; GFX6:       ; %bb.0:
1338 …XT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x255 ; encoding: [0x01,0x38,0x80,0xba,0x55,0x…
1341 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1344 ; GFX789:       ; %bb.0:
1345 …XT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x255 ; encoding: [0x01,0x38,0x00,0xba,0x55,0x…
1348 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1351 ; GFX10:       ; %bb.0:
1352 ; GFX10-NEXT:    s_round_mode 0x5 ; encoding: [0x05,0x00,0xa4,0xbf]
1355 ; GFX10-NEXT:    s_denorm_mode 5 ; encoding: [0x05,0x00,0xa5,0xbf]
1356 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1359 ; GFX11:       ; %bb.0:
1360 ; GFX11-NEXT:    s_round_mode 0x5 ; encoding: [0x05,0x00,0x91,0xbf]
1363 ; GFX11-NEXT:    s_denorm_mode 5 ; encoding: [0x05,0x00,0x92,0xbf]
1364 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1372 ; GFX6:       ; %bb.0:
1373 …    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x80,0xba,0xff,0x00,0…
1376 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1379 ; GFX789:       ; %bb.0:
1380 …    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x00,0xba,0xff,0x00,0…
1383 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1386 ; GFX10:       ; %bb.0:
1387 …    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x80,0xba,0xff,0x00,0…
1390 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1393 ; GFX11:       ; %bb.0:
1394 …    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x80,0xb9,0xff,0x00,0…
1397 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1405 ; GFX6:       ; %bb.0:
1406 …setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x80,0xba,0x0f,0x00,0x00,0x00]
1409 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1412 ; GFX789:       ; %bb.0:
1413 …setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x00,0xba,0x0f,0x00,0x00,0x00]
1416 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1419 ; GFX10:       ; %bb.0:
1420 …setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x80,0xba,0x0f,0x00,0x00,0x00]
1423 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1426 ; GFX11:       ; %bb.0:
1427 …setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x80,0xb9,0x0f,0x00,0x00,0x00]
1430 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1438 ; GFX6:       ; %bb.0:
1439 ; GFX6-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9]
1442 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1445 ; GFX789:       ; %bb.0:
1446 ; GFX789-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9]
1449 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1452 ; GFX10:       ; %bb.0:
1453 ; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9]
1456 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1459 ; GFX11:       ; %bb.0:
1460 ; GFX11-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9]
1463 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1471 ; GFX6:       ; %bb.0:
1472 ; GFX6-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9]
1475 ; GFX6-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1478 ; GFX789:       ; %bb.0:
1479 ; GFX789-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9]
1482 ; GFX789-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1485 ; GFX10:       ; %bb.0:
1486 ; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x80,0xb9]
1489 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1492 ; GFX11:       ; %bb.0:
1493 ; GFX11-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE), s0 ; encoding: [0x01,0xf8,0x00,0xb9]
1496 ; GFX11-NEXT:    s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
1509 declare void @llvm.amdgcn.s.setreg(i32 immarg, i32) #0
1511 attributes #0 = { nounwind }