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/freebsd-src/sys/contrib/device-tree/src/powerpc/
H A Dmicrowatt.dts4 #size-cells = <0x02>;
5 #address-cells = <0x02>;
14 #size-cells = <0x02>;
15 #address-cells = <0x02>;
19 memory@0 {
21 reg = <0x00000000 0x00000000 0x00000000 0x10000000>;
26 #clock-cells = <0>;
33 #size-cells = <0x00>;
34 #address-cells = <0x01>;
70 isa = <0>;
[all …]
H A Dmpc7448hpc2.dts29 #size-cells =<0>;
31 PowerPC,7448@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K bytes
37 i-cache-size = <0x8000>; // L1, 32K bytes
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 clock-frequency = <0>; // From U-Boot
40 bus-frequency = <0>; // From U-Boot
46 reg = <0x0 0x20000000 // DDR2 512M at 0
54 ranges = <0x0 0xc0000000 0x10000>;
[all …]
H A Dholly.dts23 #size-cells =<0>;
24 PowerPC,750CL@0 {
26 reg = <0x00000000>;
39 memory@0 {
41 reg = <0x00000000 0x20000000>;
49 ranges = <0x00000000 0xc0000000 0x00010000>;
50 reg = <0xc0000000 0x00010000>;
56 interrupts = <0xe 0x2>;
57 reg = <0x00007000 0x00000400>;
62 reg = <0x00006000 0x00000050>;
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/media/
H A Dmediatek,vcodec-decoder.yaml151 reg = <0x16020000 0x1000>, /*VDEC_MISC*/
152 <0x16021000 0x800>, /*VDEC_LD*/
153 <0x16021800 0x800>, /*VDEC_TOP*/
154 <0x16022000 0x1000>, /*VDEC_CM*/
155 <0x16023000 0x1000>, /*VDEC_AD*/
156 <0x16024000 0x1000>, /*VDEC_AV*/
157 <0x16025000 0x1000>, /*VDEC_PP*/
158 <0x16026800 0x800>, /*VP8_VD*/
159 <0x16027000 0x800>, /*VP6_VD*/
160 <0x16027800 0x800>, /*VP8_VL*/
[all …]
H A Dmediatek-vcodec.txt38 reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/
39 <0 0x16020000 0 0x1000>, /*VDEC_MISC*/
40 <0 0x16021000 0 0x800>, /*VDEC_LD*/
41 <0 0x16021800 0 0x800>, /*VDEC_TOP*/
42 <0 0x16022000 0 0x1000>, /*VDEC_CM*/
43 <0 0x16023000 0 0x1000>, /*VDEC_AD*/
44 <0 0x16024000 0 0x1000>, /*VDEC_AV*/
45 <0 0x16025000 0 0x1000>, /*VDEC_PP*/
46 <0 0x16026800 0 0x800>, /*VP8_VD*/
47 <0 0x16027000 0 0x800>, /*VP6_VD*/
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/hsi/
H A Domap-ssi.txt37 0 and 1 (in this order).
55 reg = <0x48058000 0x1000>,
56 <0x48059000 0x1000>;
77 reg = <0x4805a000 0x800>,
78 <0x4805a800 0x800>;
92 reg = <0x4805b000 0x800>,
93 <0x4805b800 0x800>;
/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dlitex,liteeth.yaml56 minimum: 0x800
57 default: 0x800
78 reg = <0x8021000 0x100>,
79 <0x8020800 0x100>,
80 <0x8030000 0x2000>;
84 litex,slot-size = <0x800>;
85 interrupts = <0x11 0x1>;
90 #size-cells = <0>;
92 eth_phy: ethernet-phy@0 {
93 reg = <0>;
/freebsd-src/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp.dtsi35 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
41 reg = <0x1400 0x500>;
46 reg = <0x08000 0x1000>;
47 cache-id-part = <0x100>;
55 pinctrl-0 = <&uart2_pins>;
57 reg = <0x12200 0x100>;
61 clocks = <&coreclk 0>;
67 pinctrl-0 = <&uart3_pins>;
69 reg = <0x12300 0x100>;
73 clocks = <&coreclk 0>;
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/timer/
H A Dsamsung,exynos4210-mct.yaml68 0: Global Timer Interrupt 0
72 4: Local Timer Interrupt 0
166 reg = <0x10050000 0x800>;
186 reg = <0x101C0000 0x800>;
207 reg = <0x1005000
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2g-netcp.dtsi13 power-domains = <&k2g_pds 0x0018>;
14 clocks = <&k2g_clks 0x0018 0>;
17 queue-range = <0 0x80>;
18 linkram0 = <0x4020000 0x7ff>;
26 managed-queues = <0 0x80>;
27 reg = <0x410000
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp157.dtsi13 reg = <0x59000000 0x800>;
22 reg = <0x5a000000 0x800>;
32 #size-cells = <0>;
34 port@0 {
35 reg = <0>;
/freebsd-src/sys/contrib/device-tree/Bindings/display/panel/
H A Dorisetech,otm8009a.yaml7 title: Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode)
13 The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using
44 #size-cells = <0>;
45 panel@0 {
47 reg = <0>;
48 reset-gpios = <&gpiof 15 0>;
/freebsd-src/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mvebu-utmi.txt23 - #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be 0.
30 reg = <0x5f000 0x800>;
32 #phy-cells = <0>;
37 reg = <0x5f800 0x800>;
H A Dmarvell,armada-3700-utmi-phy.yaml28 const: 0
49 reg = <0x5f000 0x800>;
51 #phy-cells = <0>;
56 reg = <0x5f800 0x800>;
/freebsd-src/sys/dev/dpaa2/
H A Ddpaa2_mcp.h41 #define DPAA2_MCP_MEM_WIDTH 0x40 /* Minimal size of the MC portal. */
49 #define DPAA2_PORTAL_DEF 0x0u
50 #define DPAA2_PORTAL_NOWAIT_ALLOC 0x2u /* Do not sleep during init */
51 #define DPAA2_PORTAL_LOCKED 0x4000u /* Wait till portal's unlocked */
52 #define DPAA2_PORTAL_DESTROYED 0x8000u /* Terminate any operations */
55 #define DPAA2_CMD_DEF 0x0u
56 #define DPAA2_CMD_HIGH_PRIO 0x80u /* High priority command */
57 #define DPAA2_CMD_INTR_DIS 0x100u /* Disable cmd finished intr */
58 #define DPAA2_CMD_NOWAIT_ALLOC 0x8000u /* Do not sleep during init */
61 #define DPAA2_CMD_STAT_OK 0x0 /* Set by MC on success */
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/microchip/
H A Dsam9x60.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0
[all...]
H A Dsama7g5.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
88 hysteresis = <0>;
94 hysteresis = <0>;
100 hysteresis = <0>;
122 #clock-cells = <0>;
127 #clock-cells = <0>;
132 #clock-cells = <0>;
151 reg = <0x10000
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/omap/
H A Dl4.txt27 reg = <0x48000000 0x800>,
28 <0x48000800 0x800>,
29 <0x48001000 0x400>,
30 <0x48001400 0x400>,
31 <0x48001800 0x400>,
32 <0x48001c00 0x400>;
36 ranges = <0 0x48000000 0x100000>;
/freebsd-src/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/freebsd-src/sys/isa/
H A Dpnp.c66 * The Gravis UltraSound needs register 0xf2 to be set to 0xff
70 { 0x0100561e /* GRV0001 */, 0,
71 PNP_QUIRK_WRITE_REG, 0xf2, 0xff },
76 { 0x26008c0e /* SB16 */, 0x21008c0e,
77 PNP_QUIRK_EXTRA_IO, 0x400, 0x80
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/bcm/
H A Dbrcm,brcmstb.txt49 ranges = <0 0x00 0xf0000000 0x1000000>;
53 reg = <0x404000 0x51c>;
58 reg = <0x3e2400 0x5b4>;
64 reg = <0x452000 0x100>;
94 syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
117 syscon = <&sun_top_ctrl 0x304 0x308>;
141 reg = <0x410000 0x400>;
170 "brcm,brcmstb-ddr-phy-v72.0"
182 - compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
199 memc@0 {
[all …]
/freebsd-src/sys/riscv/riscv/
H A Delf_machdep.c75 .sv_maxuser = 0, /* Filled in during boot. */
76 .sv_usrstack = 0, /* Filled in during boot. */
77 .sv_psstrings = 0, /* Filled in during boot. */
90 .sv_shared_page_base = 0, /* Filled in during boot. */
141 SYSCTL_BOOL(_debug, OID_AUTO, kld_reloc, CTLFLAG_RW, &debug_kld, 0,
165 mask = ~0; in gen_bitmask()
169 if (lsb > 0) in gen_bitmask()
224 * For example, 0x123800 can be calculated by adding upper 20 bit of
225 * 0x124000 and sign-extended 12bit immediate whose bit pattern is
226 * 0x800 as follows:
[all …]
/freebsd-src/sys/dev/drm2/
H A Ddrm_pciids.h14 {0, 0, 0, NULL}
17 {0x3D3D, 0x0008, 0, "3DLabs GLINT Gamma G1"}, \
18 {0, 0, 0, NULL}
21 {0x8086, 0x1132, 0, "Intel i815 GMCH"}, \
22 {0x8086, 0x7121, 0, "Intel i810 GMCH"}, \
23 {0x8086, 0x7123, 0, "Intel i810-DC100 GMCH"}, \
24 {0x8086, 0x7125, 0, "Intel i810E GMCH"}, \
25 {0, 0, 0, NULL}
28 {0x8086, 0x2562, 0, "Intel i845G GMCH"}, \
29 {0x8086, 0x2572, 0, "Intel i865G GMCH"}, \
[all …]
H A Ddrm_edid_modes.h36 736, 832, 0, 350, 382, 385, 445, 0,
40 736, 832, 0, 400, 401, 404, 445, 0,
44 828, 936, 0, 400, 401, 404, 446, 0,
48 752, 800, 0, 480, 489, 492, 525, 0,
52 704, 832, 0, 480, 489, 492, 520, 0,
56 720, 840, 0, 480, 481, 484, 500, 0,
60 752, 832, 0, 480, 481, 484, 509, 0,
64 896, 1024, 0, 600, 601, 603, 625, 0,
68 968, 1056, 0, 600, 601, 605, 628, 0,
72 976, 1040, 0, 600, 637, 643, 666, 0,
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm-ns.dtsi26 ranges = <0x00000000 0x18000000 0x00001000>;
32 reg = <0x0300 0x100>;
40 reg = <0x0400 0x100>;
44 pinctrl-0 = <&pinmux_uart1>;
51 ranges = <0x00000000 0x19000000 0x00023000>;
57 reg = <0x20000 0x100>;
62 reg = <0x20200 0x100>;
69 reg = <0x20600 0x20>;
78 #address-cells = <0>;
80 reg = <0x21000 0x1000>,
[all …]

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