Lines Matching +full:0 +full:x800
66 * The Gravis UltraSound needs register 0xf2 to be set to 0xff
70 { 0x0100561e /* GRV0001 */, 0,
71 PNP_QUIRK_WRITE_REG, 0xf2, 0xff },
76 { 0x26008c0e /* SB16 */, 0x21008c0e,
77 PNP_QUIRK_EXTRA_IO, 0x400, 0x800 },
78 { 0x42008c0e /* SB32(CTL0042) */, 0x21008c0e,
79 PNP_QUIRK_EXTRA_IO, 0x400, 0x800 },
80 { 0x44008c0e /* SB32(CTL0044) */, 0x21008c0e,
81 PNP_QUIRK_EXTRA_IO, 0x400, 0x800 },
82 { 0x49008c0e /* SB32(CTL0049) */, 0x21008c0e,
83 PNP_QUIRK_EXTRA_IO, 0x400, 0x800 },
84 { 0xf1008c0e /* SB32(CTL00f1) */, 0x21008c0e,
85 PNP_QUIRK_EXTRA_IO, 0x400, 0x800 },
86 { 0xc1008c0e /* SB64(CTL00c1) */, 0x22008c0e,
87 PNP_QUIRK_EXTRA_IO, 0x400, 0x800 },
88 { 0xc5008c0e /* SB64(CTL00c5) */, 0x22008c0e,
89 PNP_QUIRK_EXTRA_IO, 0x400, 0x800 },
90 { 0xe4008c0e /* SB64(CTL00e4) */, 0x22008c0e,
91 PNP_QUIRK_EXTRA_IO, 0x400, 0x800 },
93 { 0 }
120 outb(_PNP_ADDRESS, 0);
121 outb(_PNP_ADDRESS, 0); /* yes, we do need it twice! */
123 cur = 0x6a;
127 cur = (cur >> 1) | (((cur ^ (cur >> 1)) << 7) & 0xff);
139 int i, bit, valid = 0, sum = 0x6a;
144 for (i = 0; i < 72; i++) {
145 bit = inb((pnp_rd_port << 2) | 0x3) == 0x55;
149 bit = (inb((pnp_rd_port << 2) | 0x3) == 0xaa) && bit;
155 (((sum ^ (sum >> 1) ^ bit) << 7) & 0xff);
156 data[i / 8] = (data[i / 8] >> 1) | (bit ? 0x80 : 0);
174 count = 0;
175 for (i = 0; i < len; i++) {
177 for (j = 0; j < 100; j++) {
178 if ((inb((pnp_rd_port << 2) | 0x3)) & 0x1)
187 temp = inb((pnp_rd_port << 2) | 0x3);
245 for (i = 0; i < config->ic_nmem; i++) {
250 if (config->ic_mem[i].ir_size == 0) {
251 pnp_write(PNP_MEM_BASE_HIGH(i), 0);
252 pnp_write(PNP_MEM_BASE_LOW(i), 0);
253 pnp_write(PNP_MEM_RANGE_HIGH(i), 0);
254 pnp_write(PNP_MEM_RANGE_LOW(i), 0);
258 if (start & 0xff)
260 pnp_write(PNP_MEM_BASE_HIGH(i), (start >> 16) & 0xff);
261 pnp_write(PNP_MEM_BASE_LOW(i), (start >> 8) & 0xff);
262 pnp_write(PNP_MEM_RANGE_HIGH(i), (size >> 16) & 0xff);
263 pnp_write(PNP_MEM_RANGE_LOW(i), (size >> 8) & 0xff);
267 pnp_write(PNP_MEM_BASE_HIGH(i), 0);
268 pnp_write(PNP_MEM_BASE_LOW(i), 0);
269 pnp_write(PNP_MEM_RANGE_HIGH(i), 0);
270 pnp_write(PNP_MEM_RANGE_LOW(i), 0);
273 for (i = 0; i < config->ic_nport; i++) {
276 if (config->ic_port[i].ir_size == 0) {
277 pnp_write(PNP_IO_BASE_HIGH(i), 0);
278 pnp_write(PNP_IO_BASE_LOW(i), 0);
281 pnp_write(PNP_IO_BASE_HIGH(i), (start >> 8) & 0xff);
282 pnp_write(PNP_IO_BASE_LOW(i), (start >> 0) & 0xff);
286 pnp_write(PNP_IO_BASE_HIGH(i), 0);
287 pnp_write(PNP_IO_BASE_LOW(i), 0);
290 for (i = 0; i < config->ic_nirq; i++) {
294 if (config->ic_irqmask[i] == 0) {
295 pnp_write(PNP_IRQ_LEVEL(i), 0);
305 * IRQ 0 is not a valid interrupt selection and
308 pnp_write(PNP_IRQ_LEVEL(i), 0);
312 for (i = 0; i < config->ic_ndrq; i++) {
315 if (config->ic_drqmask[i] == 0) {
330 pnp_write(PNP_ACTIVATE, enable ? 1 : 0);
347 for (qp = &pnp_quirks[0]; qp->vendor_id; qp++) {
349 && (qp->logical_id == 0 || qp->logical_id == logical_id)) {
358 if (qp->arg1 != 0) {
360 config->ic_port[config->ic_nport - 1] = config->ic_port[0];
364 if (qp->arg2 != 0) {
366 config->ic_port[config->ic_nport - 1] = config->ic_port[0];
390 device_t dev = 0;
391 int ldn = 0;
397 while (scanning > 0) {
400 if (PNP_RES_TYPE(tag) != 0) {
403 scanning = 0;
406 large_len = resp[0] + (resp[1] << 8);
410 scanning = 0;
436 buf[large_len] = '\0';
446 scanning = 0;
462 dev = 0;
486 scanning = 0;
502 scanning = 0;
507 dev = 0;
509 scanning = 0;
541 if (space == 0) {
571 return (0);
586 int len = 0;
590 error = 0;
591 done = 0;
597 if (PNP_RES_TYPE(tag) == 0) {
644 int found = 0, len;
646 int space = 0;
663 pnp_write(PNP_WAKE, 0);
705 pnp_write(PNP_WAKE, 0);
740 /* Try various READ_DATA ports from 0x203-0x3ff */
741 for (pnp_rd_port = 0x80; (pnp_rd_port < 0xff); pnp_rd_port += 0x10) {
744 (pnp_rd_port << 2) | 0x3);
758 { 0, 0 }
767 DRIVER_MODULE(pnp, isa, pnp_driver, 0, 0);