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/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dconvert-rr-to-ri-instrs-kill-flag.mir9 bb.0.entry:
10 liveins: $x3, $f1, $x5
12 STFSX killed $f1, $x3, $x5
13 ; CHECK: STFS killed $f1, 100, $x5
14 STD killed $x3, killed $x5, 100
15 ; CHECK: STD killed $x3, killed $x5, 100
26 bb.0.entry:
27 liveins: $x3, $f1, $x5
30 STFSX killed $f1, killed $x3, killed $x5
31 ; CHECK: STFS killed $f1, 100, killed $x5
[all …]
H A Dmachine-backward-cp.mir12 bb.0.entry:
29 ; CHECK: bb.0.entry:
36 bb.0.entry:
39 renamable $x5 = LI8 42
40 renamable $x4 = COPY renamable killed $x5
56 bb.0.entry:
73 bb.0.entry:
75 ; CHECK: renamable $x4 = LI8 0
76 ; CHECK: renamable $x5 = ADDI8 $x4, 1
79 renamable $x4 = LI8 0
[all …]
H A Dtopdepthreduce-postra.mir5 # because of the dependency on x5
8 bb.0:
10 ; CHECK: renamable $x5 = LD 0, killed renamable $x5 :: (load (s64))
11 ; CHECK: renamable $x4 = LD 0, killed renamable $x4 :: (load (s64))
12 ; CHECK: renamable $x5 = MULLD killed renamable $x5, renamable $x3
13 … ; CHECK: renamable $x3 = MADDLD8 killed renamable $x4, killed renamable $x3, killed renamable $x5
14 renamable $x5 = LD 0, killed renamable $x5 :: (load (s64))
15 renamable $x5 = MULLD killed renamable $x5, renamable $x3
16 renamable $x4 = LD 0, killed renamable $x4 :: (load (s64))
17 renamable $x3 = MADDLD8 killed renamable $x4, killed renamable $x3, killed renamable $x5
H A Dconvert-rr-to-ri-instr-add.mir9 bb.0.entry:
10 liveins: $x3, $f1, $x5
11 $x3 = ADDI8 $x5, 100
13 ; CHECK: STFS killed $f1, 100, $x5
14 STD killed $x3, killed $x5, 100
15 ; CHECK: STD killed $x3, killed $x5, 100
24 bb.0.entry:
25 liveins: $x3, $f1, $x5
26 $x3 = ADDI8 $x5, 100
28 ; CHECK: $x3 = ADDI8 $x5, 100, implicit-def $r3
[all …]
H A Dmacro-fusion.mir7 # CHECK: add_mulld:%bb.0
8 # CHECK: Macro fuse: SU(0) - SU(1) / MULLD - ADD8
13 bb.0.entry:
14 liveins: $x3, $x4, $x5
16 renamable $x3 = ADD8 killed renamable $x4, $x5
20 # CHECK: add_and:%bb.0
21 # CHECK: Macro fuse: SU(0) - SU(1) / ADD8 - AND8
26 bb.0.entry:
27 liveins: $x3, $x4, $x5
29 renamable $x3 = AND8 killed renamable $x4, $x5
[all …]
H A Dexpand-isel-liveness.mir
H A Dremove-self-copies.mir28 %add12 = select i1 %cmp7, i32 %a, i32 0
33 %retval.0 = phi i32 [ %add, %if.then5 ], [ %c, %entry ], [ %b, %if.end ]
34 ret i32 %retval.0
51 - { reg: '$x5', virtual-reg: '' }
57 stackSize: 0
58 offsetAdjustment: 0
59 maxAlignment: 0
63 maxCallFrameSize: 0
67 localFrameSize: 0
74 bb.0.entry:
[all …]
H A Dblock-placement.mir12 …ualsEPKvS2_(ptr nocapture readnone %this, ptr readonly %key1, ptr readonly %key2) unnamed_addr #0 {
20 %0 = bitcast ptr %key2 to ptr
23 %3 = load i16, ptr %0, align 2
38 %tobool.i = icmp eq i16 %5, 0
47 %tobool6.i = icmp eq i16 %7, 0
63 %tobool10.i = icmp eq i16 %8, 0
75 …%retval.0.i1 = phi i64 [ 1, %if.else.i ], [ 0, %land.lhs.true.i ], [ 0, %land.lhs.true5.i ], [ 0, …
76 %backToBool = trunc i64 %retval.0.i1 to i1
80 attributes #0 = { "target-cpu"="pwr9" }
96 - { reg: '$x5', virtual-reg: '' }
[all …]
H A Dreg_copy.mir8 bb.0.entry:
22 bb.0.entry:
36 bb.0.entry:
49 bb.0.entry:
53 ; CHECK: $x5 = MFOCRF8 $cr0
54 ; CHECK: $x5 = RLWINM8 killed $x5, 4, 28, 31, implicit-def $x3
57 renamable $x5 = COPY killed renamable $cr0, implicit-def $x3
63 bb.0.entry:
67 ; CHECK: $x5 = MFOCRF8 $cr3
68 ; CHECK: $x5 = RLWINM8 killed $x5, 16, 28, 31, implicit-def $x3
[all …]
/llvm-project/llvm/test/MC/AArch64/
H A Darmv8.9a-the.s16 // CHECK: mrs x3, RCWMASK_EL1 // encoding: [0xc3,0xd0,0x38,0xd5]
19 // CHECK: msr RCWMASK_EL1, x1 // encoding: [0xc1,0xd0,0x18,0xd5]
22 // CHECK: mrs x3, RCWSMASK_EL1 // encoding: [0x63,0xd0,0x38,0xd5]
25 // CHECK: msr RCWSMASK_EL1, x1 // encoding: [0x61,0xd0,0x18,0xd5]
29 // CHECK: rcwcas x0, x1, [x4] // encoding: [0x81,0x08,0x20,0x19]
32 // CHECK: rcwcasa x0, x1, [x4] // encoding: [0x81,0x08,0xa0,0x19]
35 // CHECK: rcwcasal x0, x1, [x4] // encoding: [0x81,0x08,0xe0,0x19]
38 // CHECK: rcwcasl x0, x1, [x4] // encoding: [0x81,0x08,0x60,0x19]
40 rcwcas x3, x5, [sp]
41 // CHECK: rcwcas x3, x5, [sp] // encoding: [0xe5,0x0b,0x23,0x19]
[all …]
H A Darmv8.1a-atomic.s11 //CHECK: casb w0, w1, [x2] // encoding: [0x41,0x7c,0xa0,0x08]
12 //CHECK: casab w0, w1, [x2] // encoding: [0x41,0x7c,0xe0,0x08]
13 //CHECK: caslb w0, w1, [x2] // encoding: [0x41,0xfc,0xa0,0x08]
14 //CHECK: casalb w0, w1, [x2] // encoding: [0x41,0xfc,0xe0,0x08]
31 //CHECK: cash w0, w1, [x2] // encoding: [0x41,0x7c,0xa0,0x48]
32 //CHECK: casah w0, w1, [x2] // encoding: [0x41,0x7c,0xe0,0x48]
33 //CHECK: caslh w0, w1, [x2] // encoding: [0x41,0xfc,0xa0,0x48]
34 //CHECK: casalh w0, w1, [x2] // encoding: [0x41,0xfc,0xe0,0x48]
42 //CHECK: cas w0, w1, [x2] // encoding: [0x41,0x7c,0xa0,0x88]
43 //CHECK: casa w0, w1, [x2] // encoding: [0x41,0x7c,0xe0,0x88]
[all …]
H A Darm32-elf-relocs.s10 // CHECK-OBJ-ILP32: 0 R_AARCH64_P32_ADD_ABS_LO12_NC sym
12 add x5, x7, #:dtprel_lo12:sym
13 // CHECK: add x5, x7, :dtprel_lo12:sym
28 add x5, x0, #:tlsdesc_lo12:sym
29 // CHECK: add x5, x0, :tlsdesc_lo12:sym
34 // CHECK-OBJ-ILP32: 18 R_AARCH64_P32_ADD_ABS_LO12_NC sym+0x8
36 add x5, x7, #:dtprel_lo12:sym+1
37 // CHECK: add x5, x7, :dtprel_lo12:sym+1
38 // CHECK-OBJ-ILP32: 1c R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 sym+0x1
42 // CHECK-OBJ-ILP32:20 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC sym+0x2
[all …]
/llvm-project/llvm/test/tools/llvm-dwarfdump/X86/
H A Dprettyprint_types.s60 # tv<bool, true>, tv<bool, false>, tv<short, 0>, tv<unsigned short, 0>,
61 # tv<int, 0>, tv<long, 0L>, tv<long long, 0LL>, tv<unsigned, 0U>,
62 # tv<unsigned long, 0UL>, tv<unsigned long long, 0ULL>
143 # CHECK: DW_AT_type{{.*}}"tv<e1, (e1)0>")
145 # CHECK: DW_AT_type{{.*}}"tv<e2, (e2)0>")
156 # CHECK: DW_AT_type{{.*}}"tv<short, (short)0>"
157 # CHECK: DW_AT_type{{.*}}"tv<unsigned short, (unsigned short)0>"
158 # CHECK: DW_AT_type{{.*}}"tv<int, 0>"
159 # CHECK: DW_AT_type{{.*}}"tv<long, 0L>"
160 # CHECK: DW_AT_type{{.*}}"tv<long long, 0LL>"
[all …]
H A Dsimplified-template-names.s13 …file 0 "/usr/local/google/home/blaikie/dev/llvm/src" "cross-project-tests/debuginfo-tests/clang_ll…
14 .file 1 "/usr" "include/x86_64-linux-gnu/bits/types.h" md5 0x58b79843d97f4309eefa4aa722dac91e
15 .file 2 "/usr" "include/x86_64-linux-gnu/bits/stdint-intn.h" md5 0xb26974ec56196748bbc399ee826d2a0e
17 .file 4 "/usr" "include/stdint.h" md5 0x8e56ab3ccd56760d8ae9848ebf326071
18 ….file 5 "/usr" "include/x86_64-linux-gnu/bits/stdint-uintn.h" md5 0x3d2fbc5d847dd222c2fbd704575684…
20 .p2align 4, 0x90
24 ….loc 0 142 0 # cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/si…
26 # %bb.0:
34 ….loc 0 142 44 prologue_end # cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/si…
44 .p2align 4, 0x90
[all …]
/llvm-project/llvm/test/tools/llvm-objdump/X86/
H A Ddisassemble-same-section-addr.test8 # RUN: yaml2obj %s --docnum=1 -o %t1 -D SIZE1=0 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS
10 # RUN: yaml2obj %s --docnum=1 -o %t2 -D SIZE1=0 -D SIZE2=0 -D SECTION=.first -D INDEX=SHN_ABS
14 # RUN: yaml2obj %s --docnum=1 -o %t3 -D SIZE1=1 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS
16 # RUN: yaml2obj %s --docnum=1 -o %t4 -D SIZE1=0 -D SIZE2=1 -D SECTION=.first -D INDEX=SHN_ABS
20 # RUN: yaml2obj %s --docnum=1 -o %t5 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_ABS
25 # RUN: yaml2obj %s --docnum=1 -o %t6 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_LOPROC
32 # TARGET: callq 0x5 <target>
33 # ABSOLUTE: callq 0x5 <other+0x5>
34 # FAIL: callq 0x5{{$}}
46 Address: 0x0
[all …]
/llvm-project/llvm/test/MC/Disassembler/AArch64/
H A Darmv8.9a-the.txt11 [0xc3,0xd0,0x38,0xd5]
13 [0xc1,0xd0,0x18,0xd5]
15 [0x63,0xd0,0x38,0xd5]
17 [0x61,0xd0,0x18,0xd5]
20 [0x81,0x08,0x20,0x19]
23 [0x81,0x08,0xa0,0x19]
26 [0x81,0x08,0xe0,0x19]
29 [0x81,0x08,0x60,0x19]
32 [0xe5,0x0b,0x23,0x19]
33 # CHECK: rcwcas x3, x5, [sp]
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Darm64-atomic-128.ll6 @var = global i128 0
10 ; NOOUTLINE: // %bb.0:
23 ; NOOUTLINE-NEXT: stxp w9, x4, x5, [x0]
30 ; OUTLINE: // %bb.0:
38 ; OUTLINE-NEXT: mov x3, x5
45 ; LSE: // %bb.0:
46 ; LSE-NEXT: // kill: def $x5 killed $x5 killed $x4_x5 def $x4_x5
50 ; LSE-NEXT: caspa x2, x3, x4, x5, [x0]
55 %val = extractvalue { i128, i1 } %pair, 0
61 ; NOOUTLINE: // %bb.0:
[all …]
H A Dloh.mir24 bb.0:
48 $x9 = SUBXri undef $x11, 5, 0 ; should not affect MCLOH formation
49 $x1 = ADDXri $x1, target-flags(aarch64-pageoff) @g0, 0
52 $x3 = ADDXri $x20, target-flags(aarch64-pageoff) @g0, 0
59 $x9 = ADDXri undef $x9, target-flags(aarch64-pageoff) @g0, 0
64 HINT 0, implicit def $x10 ; clobbers x10
65 $x10 = ADDXri $x10, target-flags(aarch64-pageoff) @g0, 0
71 HINT 0, implicit def $x10 ; clobbers x10
72 $x11 = ADDXri $x10, target-flags(aarch64-pageoff) @g0, 0
73 $x12 = ADDXri $x10, target-flags(aarch64-pageoff) @g0, 0
[all …]
/llvm-project/llvm/test/CodeGen/RISCV/
H A Dmachineoutliner.mir7 define i32 @outline_0(i32 %a, i32 %b) { ret i32 0 }
9 define i32 @outline_1(i32 %a, i32 %b) { ret i32 0 }
11 define i32 @outline_2(i32 %a, i32 %b) { ret i32 0 }
15 define linkonce_odr i32 @dont_outline_0(i32 %a, i32 %b) { ret i32 0 }
18 define i32 @dont_outline_1(i32 %a, i32 %b) section "named" { ret i32 0 }
20 ; Cannot outline if the X5 (t0) register is not free
21 define i32 @dont_outline_2(i32 %a, i32 %b) { ret i32 0 }
29 bb.0:
48 bb.0:
67 bb.0
[all...]
H A Dmachine-outliner-cfi.mir20 bb.0:
31 CFI_INSTRUCTION offset $x1, 0
45 bb.0:
56 CFI_INSTRUCTION offset $x1, 0
70 bb.0:
87 CFI_INSTRUCTION offset $x1, 0
H A Dmachine-outliner-position.mir21 bb.0:
48 bb.0:
75 bb.0:
H A Dmachineoutliner-pcrel-lo.mir14 @bar = dso_local local_unnamed_addr global i32 0, align 4
15 define i32 @foo(i32 %a, i32 %b) { ret i32 0 }
18 define i32 @foo2(i32 %a, i32 %b) comdat { ret i32 0 }
20 define i32 @foo3(i32 %a, i32 %b) section ".abc" { ret i32 0 }
22 define i32 @foo4(i32 %a, i32 %b) !section_prefix !0 { ret i32 0 }
23 !0 = !{!"function_section_prefix", !"myprefix"}
30 ; CHECK: bb.0:
33 ; CHECK-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_1, implicit-def $x5, implici
[all...]
/llvm-project/clang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/
H A Dp5-cxx0x-no-extra-copy.cpp5 // make a copy. C++0x does not permit the copy, so ensure that we
29 double *dp = 0; in get_value_badly()
40 struct X5 { struct
41 X5();
42 X5(const X5&, const X5& = X5());
49 void g5(const X5&);
56 g5(X5()); in test()
65 int &g(int_c<sizeof(f(T()))> * = 0); // expected-note{{candidate function [with T = X3]}}
H A Dp5-cxx03-extra-copy.cpp22 X3(); // expected-note{{requires 0 arguments, but 1 was provided}}
31 double *dp = 0; in get_value_badly()
44 struct X5 { struct
45 X5();
46 …X5(const X5&, const X5& = X5()); // expected-error {{recursive evaluation of default argument}} ex…
53 void g5(const X5&);
60 g5(X5()); in test()
71 int &g(int_c<sizeof(f(T()))> * = 0);
/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
H A Darm64-atomic-128.ll10 @var = global i128 0
14 ; CHECK-LLSC-O1: // %bb.0:
27 ; CHECK-LLSC-O1-NEXT: stxp w10, x4, x5, [x0]
30 ; CHECK-LLSC-O1-NEXT: mov v0.d[0], x8
36 ; CHECK-OUTLINE-LLSC-O1: // %bb.0:
45 ; CHECK-OUTLINE-LLSC-O1-NEXT: mov x3, x5
48 ; CHECK-OUTLINE-LLSC-O1-NEXT: mov v0.d[0], x0
55 ; CHECK-CAS-O1: // %bb.0:
59 ; CHECK-CAS-O1-NEXT: // kill: def $x5 killed $x5 killed $x4_x5 def $x4_x5
60 ; CHECK-CAS-O1-NEXT: caspa x2, x3, x4, x5, [x0]
[all …]

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