/llvm-project/llvm/test/MC/Mips/ |
H A D | reloc-directive.s | 19 .reloc 0, R_MIPS_NONE, foo+4 # ASM: .reloc 0, R_MIPS_NONE, foo+4 104 # OBJ-O32: 0x0 R_MIPS_NONE .text 105 # OBJ-O32-NEXT: 0x4 R_MIPS_NONE .text 106 # OBJ-O32-NEXT: 0x8 R_MIPS_32 .text 107 # OBJ-O32-NEXT: 0xC R_MIPS_NONE - 108 # OBJ-O32-NEXT: 0x10 R_MIPS_CALL_HI16 - 109 # OBJ-O32-NEXT: 0x14 R_MIPS_CALL_LO16 - 110 # OBJ-O32-NEXT: 0x18 R_MIPS_CALL16 - 111 # OBJ-O32-NEXT: 0x20 R_MIPS_GOT_PAGE - 112 # OBJ-O32-NEXT: 0x24 R_MIPS_GOT_OFST - [all …]
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/llvm-project/llvm/test/CodeGen/PowerPC/ |
H A D | machine-backward-cp.mir | 12 bb.0.entry: 16 renamable $x4 = LI8 1024 17 $x3 = COPY renamable killed $x4 29 ; CHECK: bb.0.entry: 30 ; CHECK: renamable $x4 = LI8 42 33 ; CHECK: liveins: $x4 34 ; CHECK: $x3 = COPY killed renamable $x4 36 bb.0.entry: 40 renamable $x4 = COPY renamable killed $x5 44 liveins: $x4 [all …]
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H A D | fold-frame-offset-using-rr.mir | 18 bb.0.entry: 19 liveins: $x3, $x1, $x4, $x6 22 $x4 = ADD8 killed $x3, killed $x4 24 $x6 = LD 4, killed $x4 25 ; CHECK: $x6 = LDX killed $x4, killed $x3 34 bb.0.entry: 35 liveins: $x3, $x1, $x4, $x6 38 $x3 = ADD8 killed $x3, killed $x4 41 ; CHECK: $x6 = LDX killed $x4, killed $x3 50 bb.0.entry: [all …]
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H A D | macro-fusion.mir | 7 # CHECK: add_mulld:%bb.0 8 # CHECK: Macro fuse: SU(0) - SU(1) / MULLD - ADD8 13 bb.0.entry: 14 liveins: $x3, $x4, $x5 15 renamable $x4 = MULLD $x3, $x4 16 renamable $x3 = ADD8 killed renamable $x4, $x5 20 # CHECK: add_and:%bb.0 21 # CHECK: Macro fuse: SU(0) - SU(1) / ADD8 - AND8 26 bb.0.entry: 27 liveins: $x3, $x4, $x5 [all …]
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H A D | ldst-16-byte.mir | 10 bb.0.entry: 11 liveins: $x5, $x4 13 ; CHECK: liveins: $x4, $x5 15 ; CHECK-NEXT: early-clobber renamable $g8p3 = LQ 128, $x4 19 %0:g8prc = LQ 128, $x4 20 $x5 = COPY %0.sub_gp8_x1:g8prc 21 STQ %0, 160, $x5 30 bb.0.entry: 31 liveins: $x3, $x4 [all...] |
H A D | opt-cmp-rec-postra.mir | 8 bb.0.entry: 9 successors: %bb.1(0x30000000), %bb.2(0x50000000) 10 liveins: $x3, $x4 11 renamable $x3 = OR8 killed renamable $x3, killed renamable $x4 12 renamable $cr0 = CMPDI renamable $x3, 0, implicit killed $x3 14 ; CHECK: renamable $x3 = OR8_rec killed renamable $x3, killed renamable $x4, implicit-def $cr0 29 # The imm of the comparison instr isn't 0. 32 bb.0.entry: 33 successors: %bb.1(0x30000000), %bb.2(0x50000000) 34 liveins: $x3, $x4 [all …]
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H A D | mcp-elim-eviction-chain.mir | 48 bb.0.entry: 49 liveins: $x4, $x5, $x20, $x21, $x22 51 ; CHECK: liveins: $x4, $x5, $x20, $x21, $x22 53 ; CHECK-NEXT: renamable $x24 = COPY $x4 55 ; CHECK-NEXT: renamable $x20 = ADD8 $x4, $x5 56 ; CHECK-NEXT: renamable $x4 = COPY renamable $x20 59 ; CHECK-NEXT: $x3 = COPY renamable $x4 61 renamable $x23 = COPY renamable $x4 66 renamable $x20 = ADD8 $x4, $x5 67 renamable $x4 = COPY renamable $x20 [all …]
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H A D | expand-isel-liveness.mir |
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H A D | remove-redundant-load-imm.mir | 10 bb.0.entry: 15 ; CHECK: renamable $x3 = LI8 0 19 renamable $x3 = LI8 0 21 renamable $x3 = LI8 0 32 bb.0.entry: 37 ; CHECK: renamable $x3 = LI8 0 43 renamable $x3 = LI8 0 45 renamable $x3 = LI8 0 47 renamable $x3 = LI8 0 49 renamable $x3 = LI8 0 [all …]
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H A D | convert-rr-to-ri-instrs-out-of-range.mir | 11 define zeroext i32 @testRLWNM(i32 zeroext %a) local_unnamed_addr #0 { 19 define i64 @testRLWNM8(i64 %a) local_unnamed_addr #0 { 27 define zeroext i32 @testRLWNM_rec(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 { 30 %tobool = icmp eq i32 %and, 0 36 define i64 @testRLWNM8_rec(i64 %a, i64 %b) local_unnamed_addr #0 { 39 %0 = shl i32 %a.tr, 4 40 %conv = and i32 %0, 4080 41 %tobool = icmp eq i32 %conv, 0 48 define zeroext i32 @testSLW(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 { 55 define zeroext i32 @testSLW_rec(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 { [all...] |
H A D | remove-redundant-li-implicit-reg.mir | 8 bb.0.entry: 9 liveins: $x3, $x4, $x5 13 renamable $x4 = exact SRD killed renamable $x4, killed renamable $r5, implicit $x5 14 STD $x4, $x4, 100 18 ; CHECK: bb.0.entry: 20 ; CHECK: renamable $x4 = exact RLDICL killed renamable $x4, 62, 2 21 ; CHECK: STD killed $x4, killed $x4, 100
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H A D | shrink-wrap.mir | 15 %cmp5 = icmp sgt i32 %lim, 0 19 %0 = add i32 %lim, -1 20 %1 = zext i32 %0 to i64 26 %Ret.0.lcssa = phi i32 [ 0, %entry ], [ %3, %for.body ] 27 ret i32 %Ret.0.lcssa 30 %Ret.06 = phi i32 [ %3, %for.body ], [ 0, %for.body.preheader ] 31 …%3 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},… 37 declare void @llvm.set.loop.iterations.i64(i64) #0 40 declare i1 @llvm.loop.decrement.i64(i64) #0 45 attributes #0 = { noduplicate nounwind } [all …]
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/llvm-project/llvm/test/MC/AArch64/ |
H A D | armv8.9a-the.s | 16 // CHECK: mrs x3, RCWMASK_EL1 // encoding: [0xc3,0xd0,0x38,0xd5] 19 // CHECK: msr RCWMASK_EL1, x1 // encoding: [0xc1,0xd0,0x18,0xd5] 22 // CHECK: mrs x3, RCWSMASK_EL1 // encoding: [0x63,0xd0,0x38,0xd5] 25 // CHECK: msr RCWSMASK_EL1, x1 // encoding: [0x61,0xd0,0x18,0xd5] 28 rcwcas x0, x1, [x4] 29 // CHECK: rcwcas x0, x1, [x4] // encoding: [0x81,0x08,0x20,0x19] 31 rcwcasa x0, x1, [x4] 32 // CHECK: rcwcasa x0, x1, [x4] // encoding: [0x81,0x08,0xa0,0x19] 34 rcwcasal x0, x1, [x4] 35 // CHECK: rcwcasal x0, x1, [x4] // encoding: [0x81,0x08,0xe0,0x19] [all …]
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H A D | arm64-memory.s | 8 ldr w5, [x4, #20] 9 ldr x4, [x3] 17 ldrb w5, [x4, #20] 41 prfm pstl3strm, [x4, x5, lsl #3] 43 ; CHECK: ldr w5, [x4, #20] ; encoding: [0x85,0x14,0x40,0xb9] 44 ; CHECK: ldr x4, [x3] ; encoding: [0x64,0x00,0x40,0xf9] 45 ; CHECK: ldr x2, [sp, #32] ; encoding: [0xe2,0x13,0x40,0xf9] 46 ; CHECK: ldr b5, [sp, #1] ; encoding: [0xe5,0x07,0x40,0x3d] 47 ; CHECK: ldr h6, [sp, #2] ; encoding: [0xe6,0x07,0x40,0x7d] 48 ; CHECK: ldr s7, [sp, #4] ; encoding: [0xe7,0x07,0x40,0xbd] [all …]
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H A D | tme-error.s | 7 tstart x4, x5 9 // CHECK-NEXT: tstart x4, x5 10 tstart x4, #1 12 // CHECK-NEXT: tstart x4, #1 20 ttest x4, x5 22 // CHECK-NEXT: ttest x4, x5 23 ttest x4, #1 25 // CHECK-NEXT: ttest x4, #1 30 tcommit x4 32 // CHECK-NEXT: tcommit x4 [all …]
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/llvm-project/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/ |
H A D | selects-inseltpoison.ll | 19 %t0 = insertelement <3 x i32> poison, i32 %val0, i32 0 30 %base.x4 = shl i32 %base, 2 31 %base.x4.p1 = add i32 %base.x4, 1 32 %base.x4.p2 = add i32 %base.x4, 2 33 %base.x4.p3 = add i32 %base.x4, 3 34 %zext.x4 = zext i32 %base.x4 to i64 35 %zext.x4.p1 = zext i32 %base.x4.p1 to i64 36 %zext.x4.p2 = zext i32 %base.x4.p2 to i64 37 %zext.x4.p3 = zext i32 %base.x4.p3 to i64 38 %base.x16 = mul i64 %zext.x4, 4 [all …]
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H A D | selects.ll | 19 %t0 = insertelement <3 x i32> undef, i32 %val0, i32 0 30 %base.x4 = shl i32 %base, 2 31 %base.x4.p1 = add i32 %base.x4, 1 32 %base.x4.p2 = add i32 %base.x4, 2 33 %base.x4.p3 = add i32 %base.x4, 3 34 %zext.x4 = zext i32 %base.x4 to i64 35 %zext.x4.p1 = zext i32 %base.x4.p1 to i64 36 %zext.x4.p2 = zext i32 %base.x4.p2 to i64 37 %zext.x4.p3 = zext i32 %base.x4.p3 to i64 38 %base.x16 = mul i64 %zext.x4, 4 [all …]
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/llvm-project/lldb/test/API/functionalities/postmortem/FreeBSDKernel/ |
H A D | kernel-i386.yaml | 8 Entry: 0x8F9000 13 Address: 0x1AB7B00 14 AddressAlign: 0x80 15 Offset: 0x12B7AB0 16 Size: 0x2D48D8 20 Address: 0x1400290 21 AddressAlign: 0x10 22 Size: 0x800 27 Value: 0x800000 31 Value: 0x1D2D9A0 [all …]
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H A D | kernel-arm64.yaml | 7 Entry: 0xFFFF000000000800 12 Address: 0xFFFF000000C35000 13 AddressAlign: 0x1000 14 Size: 0x37F000 18 Address: 0xFFFF0000008A72C0 19 AddressAlign: 0x20 20 Size: 0x1000 25 Value: 0xFFFF000000000000 29 Value: 0xFFFF000000DF3790 30 Size: 0x560 [all …]
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H A D | kernel-amd64.yaml | 8 Entry: 0xFFFFFFFF8037C000 13 Address: 0xFFFFFFFF819BA380 14 AddressAlign: 0x80 15 Offset: 0x17BA348 16 Size: 0x445C80 20 Address: 0xFFFFFFFF81152D30 21 AddressAlign: 0x10 22 Size: 0x800 27 Value: 0xFFFFFFFF80000000 32 Value: 0xFFFFFFFF81D47EB8 [all …]
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/llvm-project/llvm/test/CodeGen/AArch64/ |
H A D | arm64-atomic-128.ll | 6 @var = global i128 0 10 ; NOOUTLINE: // %bb.0: 23 ; NOOUTLINE-NEXT: stxp w9, x4, x5, [x0] 30 ; OUTLINE: // %bb.0: 37 ; OUTLINE-NEXT: mov x2, x4 39 ; OUTLINE-NEXT: mov x4, x8 45 ; LSE: // %bb.0: 48 ; LSE-NEXT: // kill: def $x4 killed $x4 killed $x4_x5 def $x4_x5 50 ; LSE-NEXT: caspa x2, x3, x4, x5, [x0] 55 %val = extractvalue { i128, i1 } %pair, 0 [all …]
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/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
H A D | armv8.9a-the.txt | 11 [0xc3,0xd0,0x38,0xd5] 13 [0xc1,0xd0,0x18,0xd5] 15 [0x63,0xd0,0x38,0xd5] 17 [0x61,0xd0,0x18,0xd5] 20 [0x81,0x08,0x20,0x19] 21 # CHECK: rcwcas x0, x1, [x4] 23 [0x81,0x08,0xa0,0x19] 24 # CHECK: rcwcasa x0, x1, [x4] 26 [0x81,0x08,0xe0,0x19] 27 # CHECK: rcwcasal x0, x1, [x4] [all …]
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/llvm-project/llvm/test/tools/llvm-objdump/ELF/RISCV/ |
H A D | extensions.test | 27 Entry: 0x380 31 VAddr: 0x34 32 Align: 0x4 37 VAddr: 0x174 38 - Type: 0x70000003 46 Align: 0x1000 51 VAddr: 0x1F04 52 Align: 0x1000 57 VAddr: 0x1F10 58 Align: 0x4 [all …]
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/llvm-project/llvm/test/tools/llvm-objdump/X86/ |
H A D | elf-disassemble-relocs.test | 7 # RUN: llvm-objdump 1.o -r --disassemble-symbols=x2,x4 | FileCheck %s --check-prefix=CHECK2 11 # RUN: llvm-objdump 1leb.o -r --disassemble-symbols=x2,x4 | FileCheck %s --check-prefix=CHECK2 15 # CHECK-NEXT: 0: e8 00 00 00 00 callq 0x5 <x1+0x5> 16 # CHECK-NEXT: 0000000000000001: R_X86_64_PC32 foo-0x4 17 # CHECK-NEXT: 0000000000000002: R_X86_64_NONE bar+0x8 18 # CHECK-NEXT: 5: e8 00 00 00 00 callq 0xa <x2> 19 # CHECK-NEXT: 0000000000000006: R_X86_64_PLT32 foo+0x1 23 # CHECK-NEXT: b: 48 8b 05 00 00 00 00 movq (%rip), %rax # 0x12 <x3> 24 # CHECK-NEXT: 000000000000000e: R_X86_64_REX_GOTPCRELX var-0x4 27 # CHECK-NEXT: 12: e8 00 00 00 00 callq 0x17 <x4> [all …]
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/llvm-project/clang/test/CXX/temp/temp.res/temp.dep/temp.dep.type/ |
H A D | p4.cpp | 333 x4; // expected-error{{use of undeclared identifier 'x4'}} in not_instantiated() 334 B::x4; // expected-error{{no member named 'x4' in 'B<T>'}} in not_instantiated() 335 A::x4; // expected-error{{no member named 'x4' in 'N0::A'}} in not_instantiated() 336 B::A::x4; // expected-error{{no member named 'x4' in 'N0::A'}} in not_instantiated() 342 this->x4; // expected-error{{no member named 'x4' i in not_instantiated() [all...] |