Lines Matching +full:0 +full:x4
11 define zeroext i32 @testRLWNM(i32 zeroext %a) local_unnamed_addr #0 {
19 define i64 @testRLWNM8(i64 %a) local_unnamed_addr #0 {
27 define zeroext i32 @testRLWNM_rec(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
30 %tobool = icmp eq i32 %and, 0
36 define i64 @testRLWNM8_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
39 %0 = shl i32 %a.tr, 4
40 %conv = and i32 %0, 4080
41 %tobool = icmp eq i32 %conv, 0
48 define zeroext i32 @testSLW(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
55 define zeroext i32 @testSLW_rec(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
58 %tobool = icmp eq i32 %shl, 0
64 define zeroext i32 @testSRW(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
71 define zeroext i32 @testSRW_rec(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
74 %tobool = icmp eq i32 %shr, 0
80 define signext i32 @testSRAW(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
87 define signext i32 @testSRAW_rec(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
90 %tobool = icmp eq i32 %shr, 0
96 define i64 @testRLDCL(i64 %a, i64 %b) local_unnamed_addr #0 {
107 define i64 @testRLDCL_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
114 %tobool = icmp eq i64 %or, 0
120 define i64 @testRLDCR(i64 %a, i64 %b) local_unnamed_addr #0 {
131 define i64 @testRLDCR_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
138 %tobool = icmp eq i64 %or, 0
143 define i64 @testSLD(i64 %a, i64 %b) local_unnamed_addr #0 {
150 define i64 @testSLD_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
153 %tobool = icmp eq i64 %shl, 0
159 define i64 @testSRD(i64 %a, i64 %b) local_unnamed_addr #0 {
166 define i64 @testSRD_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
169 %tobool = icmp eq i64 %shr, 0
175 define i64 @testSRAD(i64 %a, i64 %b) local_unnamed_addr #0 {
182 define i64 @testSRAD_rec(i64 %a, i64 %b) local_unnamed_addr #0 {
185 %tobool = icmp eq i64 %shr, 0
190 attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" }
192 !llvm.module.flags = !{!0, !1}
195 !0 = !{i32 1, !"wchar_size", i32 4}
197 !2 = !{!"clang version 6.0.0 (trunk 316067)"}
198 !3 = !{!4, !4, i64 0}
199 !4 = !{!"omnipotent char", !5, i64 0}
201 !6 = !{!7, !7, i64 0}
202 !7 = !{!"short", !4, i64 0}
203 !8 = !{!9, !9, i64 0}
204 !9 = !{!"int", !4, i64 0}
205 !10 = !{!11, !11, i64 0}
206 !11 = !{!"long long", !4, i64 0}
207 !12 = !{!13, !13, i64 0}
208 !13 = !{!"double", !4, i64 0}
209 !14 = !{!15, !15, i64 0}
210 !15 = !{!"float", !4, i64 0}
223 - { id: 0, class: g8rc, preferred-register: '' }
229 - { reg: '$x3', virtual-reg: '%0' }
235 stackSize: 0
236 offsetAdjustment: 0
237 maxAlignment: 0
251 bb.0.entry:
254 %0 = COPY $x3
255 %1 = COPY %0.sub_32
275 - { id: 0, class: g8rc, preferred-register: '' }
279 - { reg: '$x3', virtual-reg: '%0' }
285 stackSize: 0
286 offsetAdjustment: 0
287 maxAlignment: 0
301 bb.0.entry:
304 %0 = LI8 234
306 %2 = RLWNM8 %1, %0, 20, 27
323 - { id: 0, class: g8rc, preferred-register: '' }
334 - { reg: '$x3', virtual-reg: '%0' }
335 - { reg: '$x4', virtual-reg: '%1' }
341 stackSize: 0
342 offsetAdjustment: 0
343 maxAlignment: 0
357 bb.0.entry:
358 liveins: $x3, $x4
360 %1 = COPY $x4
361 %0 = COPY $x3
372 %9 = RLDICL killed %7, 0, 32
387 - { id: 0, class: g8rc, preferred-register: '' }
397 - { reg: '$x3', virtual-reg: '%0' }
398 - { reg: '$x4', virtual-reg: '%1' }
404 stackSize: 0
405 offsetAdjustment: 0
406 maxAlignment: 0
420 bb.0.entry:
421 liveins: $x3, $x4
423 %1 = COPY $x4
424 %0 = COPY $x3
430 %6 = RLDICL killed %3, 0, 32
446 - { id: 0, class: g8rc, preferred-register: '' }
456 - { reg: '$x3', virtual-reg: '%0' }
457 - { reg: '$x4', virtual-reg: '%1' }
463 stackSize: 0
464 offsetAdjustment: 0
465 maxAlignment: 0
479 bb.0.entry:
480 liveins: $x3, $x4
482 %1 = COPY $x4
483 %0 = COPY $x3
487 ; CHECK: RLWINM killed %2, 18, 0, 13
503 - { id: 0, class: g8rc, preferred-register: '' }
514 - { reg: '$x3', virtual-reg: '%0' }
515 - { reg: '$x4', virtual-reg: '%1' }
521 stackSize: 0
522 offsetAdjustment: 0
523 maxAlignment: 0
537 bb.0.entry:
538 liveins: $x3, $x4
540 %1 = COPY $x4
541 %0 = COPY $x3
543 %3 = COPY %0.sub_32
545 ; CHECK: ANDI_rec %3, 0, implicit-def $cr0
546 ; CHECK-LATE: andi. 5, 3, 0
551 %9 = RLDICL killed %7, 0, 32
566 - { id: 0, class: g8rc, preferred-register: '' }
576 - { reg: '$x3', virtual-reg: '%0' }
577 - { reg: '$x4', virtual-reg: '%1' }
583 stackSize: 0
584 offsetAdjustment: 0
585 maxAlignment: 0
599 bb.0.entry:
600 liveins: $x3, $x4
602 %1 = COPY $x4
603 %0 = COPY $x3
605 %5 = COPY %0.sub_32
607 ; CHECK: LI8 0
608 ; CHECK-LATE: li 3, 0
623 - { id: 0, class: g8rc, preferred-register: '' }
634 - { reg: '$x3', virtual-reg: '%0' }
635 - { reg: '$x4', virtual-reg: '%1' }
641 stackSize: 0
642 offsetAdjustment: 0
643 maxAlignment: 0
657 bb.0.entry:
658 liveins: $x3, $x4
660 %1 = COPY $x4
661 %0 = COPY $x3
663 %3 = COPY %0.sub_32
665 ; CHECK: ANDI_rec %3, 0, implicit-def $cr0
666 ; CHECK-LATE: andi. 5, 3, 0
671 %9 = RLDICL killed %7, 0, 32
686 - { id: 0, class: g8rc, preferred-register: '' }
693 - { reg: '$x3', virtual-reg: '%0' }
694 - { reg: '$x4', virtual-reg: '%1' }
700 stackSize: 0
701 offsetAdjustment: 0
702 maxAlignment: 0
716 bb.0.entry:
717 liveins: $x3, $x4
719 %1 = COPY $x4
720 %0 = COPY $x3
722 %3 = COPY %0.sub_32
742 - { id: 0, class: g8rc, preferred-register: '' }
751 - { reg: '$x3', virtual-reg: '%0' }
752 - { reg: '$x4', virtual-reg: '%1' }
758 stackSize: 0
759 offsetAdjustment: 0
760 maxAlignment: 0
774 bb.0.entry:
775 liveins: $x3, $x4
777 %1 = COPY $x4
778 %0 = COPY $x3
780 %3 = COPY %0.sub_32
801 - { id: 0, class: g8rc, preferred-register: '' }
807 - { reg: '$x3', virtual-reg: '%0' }
808 - { reg: '$x4', virtual-reg: '%1' }
814 stackSize: 0
815 offsetAdjustment: 0
816 maxAlignment: 0
830 bb.0.entry:
831 liveins: $x3, $x4
833 %1 = COPY $x4
834 %0 = COPY $x3
837 %4 = RLDCL %0, killed %3, 0
838 ; CHECK: RLDICL killed %0, 12, 0
854 - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
862 - { reg: '$x3', virtual-reg: '%0' }
863 - { reg: '$x4', virtual-reg: '%1' }
869 stackSize: 0
870 offsetAdjustment: 0
871 maxAlignment: 0
885 bb.0.entry:
886 liveins: $x3, $x4
888 %1 = COPY $x4
889 %0 = COPY $x3
890 %2 = RLDICL %1, 0, 58
892 %4 = RLDCL_rec %0, killed %3, 0, implicit-def $cr0
893 ; CHECK: RLDICL_rec %0, 27, 0, implicit-def $cr0
896 %6 = ISEL8 %2, %0, %5.sub_eq
911 - { id: 0, class: g8rc, preferred-register: '' }
917 - { reg: '$x3', virtual-reg: '%0' }
918 - { reg: '$x4', virtual-reg: '%1' }
924 stackSize: 0
925 offsetAdjustment: 0
926 maxAlignment: 0
940 bb.0.entry:
941 liveins: $x3, $x4
943 %1 = COPY $x4
944 %0 = COPY $x3
947 %4 = RLDCR %0, killed %3, 0
948 ; CHECK: RLDICR killed %0, 44, 0
949 ; CHECK-LATE: rldicr 3, 3, 44, 0
964 - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
972 - { reg: '$x3', virtual-reg: '%0' }
973 - { reg: '$x4', virtual-reg: '%1' }
979 stackSize: 0
980 offsetAdjustment: 0
981 maxAlignment: 0
995 bb.0.entry:
996 liveins: $x3, $x4
998 %1 = COPY $x4
999 %0 = COPY $x3
1000 %2 = RLDICL %1, 0, 58
1002 %4 = RLDCR_rec %0, killed %3, 0, implicit-def $cr0
1003 ; CHECK: RLDICR_rec %0, 46, 0, implicit-def $cr0
1004 ; CHECK-LATE: rldicr. 5, 3, 46, 0
1006 %6 = ISEL8 %2, %0, %5.sub_eq
1021 - { id: 0, class: g8rc, preferred-register: '' }
1026 - { reg: '$x3', virtual-reg: '%0' }
1027 - { reg: '$x4', virtual-reg: '%1' }
1033 stackSize: 0
1034 offsetAdjustment: 0
1035 maxAlignment: 0
1049 bb.0.entry:
1050 liveins: $x3, $x4
1052 %1 = COPY $x4
1053 %0 = COPY $x3
1055 %3 = SLD %0, killed %2
1056 ; CHECK: LI8 0
1057 ; CHECK-LATE: li 3, 0
1072 - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
1079 - { reg: '$x3', virtual-reg: '%0' }
1080 - { reg: '$x4', virtual-reg: '%1' }
1086 stackSize: 0
1087 offsetAdjustment: 0
1088 maxAlignment: 0
1102 bb.0.entry:
1103 liveins: $x3, $x4
1105 %1 = COPY $x4
1106 %0 = COPY $x3
1108 %3 = SLD_rec %0, killed %2, implicit-def $cr0
1109 ; CHECK: ANDI8_rec %0, 0, implicit-def $cr0
1110 ; CHECK-LATE: andi. 5, 3, 0
1112 %5 = ISEL8 %1, %0, %4.sub_eq
1127 - { id: 0, class: g8rc, preferred-register: '' }
1132 - { reg: '$x3', virtual-reg: '%0' }
1133 - { reg: '$x4', virtual-reg: '%1' }
1139 stackSize: 0
1140 offsetAdjustment: 0
1141 maxAlignment: 0
1155 bb.0.entry:
1156 liveins: $x3, $x4
1158 %1 = COPY $x4
1159 %0 = COPY $x3
1161 %3 = SRD %0, killed %2
1162 ; CHECK: RLDICL killed %0, 48, 16
1178 - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
1185 - { reg: '$x3', virtual-reg: '%0' }
1186 - { reg: '$x4', virtual-reg: '%1' }
1192 stackSize: 0
1193 offsetAdjustment: 0
1194 maxAlignment: 0
1208 bb.0.entry:
1209 liveins: $x3, $x4
1211 %1 = COPY $x4
1212 %0 = COPY $x3
1214 %3 = SRD_rec %0, killed %2, implicit-def $cr0
1215 ; CHECK: ANDI8_rec %0, 0, implicit-def $cr0
1216 ; CHECK-LATE: andi. 5, 3, 0
1218 %5 = ISEL8 %1, %0, %4.sub_eq
1233 - { id: 0, class: g8rc, preferred-register: '' }
1238 - { reg: '$x3', virtual-reg: '%0' }
1239 - { reg: '$x4', virtual-reg: '%1' }
1245 stackSize: 0
1246 offsetAdjustment: 0
1247 maxAlignment: 0
1261 bb.0.entry:
1262 liveins: $x3, $x4
1264 %1 = COPY $x4
1265 %0 = COPY $x3
1267 %3 = SRAD %0, killed %2, implicit-def dead $carry
1268 ; CHECK: SRAD killed %0, killed %2, implicit-def dead $carry
1284 - { id: 0, class: g8rc, preferred-register: '' }
1291 - { reg: '$x3', virtual-reg: '%0' }
1292 - { reg: '$x4', virtual-reg: '%1' }
1298 stackSize: 0
1299 offsetAdjustment: 0
1300 maxAlignment: 0
1314 bb.0.entry:
1315 liveins: $x3, $x4
1317 %1 = COPY $x4
1318 %0 = COPY $x3
1320 %3 = SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
1321 ; CHECK: SRAD_rec killed %0, killed %2, implicit-def dead $carry, implicit-def $cr0