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/llvm-project/llvm/test/tools/llvm-cvtres/
H A Dmachine.test34 X86: Machine: IMAGE_FILE_MACHINE_I386 (0x14C)
37 X86-NEXT: 0x1E8 IMAGE_REL_I386_DIR32NB $R000000
38 X86-NEXT: 0x198 IMAGE_REL_I386_DIR32NB $R000001
39 X86-NEXT: 0x1A8 IMAGE_REL_I386_DIR32NB $R000002
40 X86-NEXT: 0x1C8 IMAGE_REL_I386_DIR32NB $R000003
41 X86-NEXT: 0x1D8 IMAGE_REL_I386_DIR32NB $R000004
42 X86-NEXT: 0x1F8 IMAGE_REL_I386_DIR32NB $R000005
43 X86-NEXT: 0x1B8 IMAGE_REL_I386_DIR32NB $R000006
44 X86-NEXT: 0x188 IMAGE_REL_I386_DIR32NB $R000007
46 X64: Machine: IMAGE_FILE_MACHINE_AMD64 (0x8664)
[all …]
H A Dobject.test18 CHECK-NEXT: Table Offset: 0x38
20 CHECK-NEXT: Number of ID Entries: 0
22 CHECK-NEXT: Table Offset: 0xC8
23 CHECK-NEXT: Number of String Entries: 0
26 CHECK-NEXT: Entry Offset: 0x188
27 CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0)
28 CHECK-NEXT: Major Version: 0
29 CHECK-NEXT: Minor Version: 0
30 CHECK-NEXT: Characteristics: 0
32 CHECK-NEXT: DataRVA: 0x0
[all …]
/llvm-project/llvm/test/tools/llvm-objdump/ELF/RISCV/
H A Dextensions.test27 Entry: 0x380
31 VAddr: 0x34
32 Align: 0x4
37 VAddr: 0x174
38 - Type: 0x70000003
46 Align: 0x1000
51 VAddr: 0x1F04
52 Align: 0x1000
57 VAddr: 0x1F10
58 Align: 0x4
[all …]
/llvm-project/llvm/test/MC/MachO/ARM/
H A Ddarwin-ARM-reloc.s20 .long 0
29 @ CHECK: Magic: Magic (0xFEEDFACE)
30 @ CHECK: CpuType: Arm (0xC)
31 @ CHECK: CpuSubType: CPU_SUBTYPE_ARM_V7 (0x9)
32 @ CHECK: FileType: Relocatable (0x1)
35 @ CHECK: Flags [ (0x2000)
36 @ CHECK: MH_SUBSECTIONS_VIA_SYMBOLS (0x2000)
41 @ CHECK: Index: 0
44 @ CHECK: Address: 0x0
45 @ CHECK: Size: 0x8
[all …]
/llvm-project/llvm/test/tools/llvm-readobj/ELF/
H A Dstackmap.test13 # EMPTY-NEXT: Num Functions: 0
14 # EMPTY-NEXT: Num Constants: 0
15 # EMPTY-NEXT: Num Records: 0
26 ContentArray: [ [[VERSION=0x3]] ]
33 ContentArray: [ 0xFF ]
34 Size: 0x1
50 # RUN: yaml2obj %s -DSHSIZE=0 -o %t.trunc0
51 …llvm-readobj %t.trunc0 --stackmap 2>&1 | FileCheck %s -DFILE=%t.trunc0 --check-prefix=TRUNC -DVAL=0
52 …llvm-readelf %t.trunc0 --stackmap 2>&1 | FileCheck %s -DFILE=%t.trunc0 --check-prefix=TRUNC -DVAL=0
81 # RUN: yaml2obj %s -DSHOFFSET=0xffff -o %t.offset
[all …]
/llvm-project/lld/test/ELF/
H A Dbasic-aarch64.s12 svc 0
17 # CHECK-NEXT: Class: 64-bit (0x2)
18 # CHECK-NEXT: DataEncoding: LittleEndian (0x1)
20 # CHECK-NEXT: OS/ABI: FreeBSD (0x9)
21 # CHECK-NEXT: ABIVersion: 0
24 # CHECK-NEXT: Type: Executable (0x2)
25 # CHECK-NEXT: Machine: EM_AARCH64 (0xB7)
27 # CHECK-NEXT: Entry: [[ENTRY:0x[0-9A-F]+]]
28 # CHECK-NEXT: ProgramHeaderOffset: 0x4
[all...]
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Daix-xcoff-reloc.ll25 %0 = load i32, ptr @globalA, align 4
26 %add = add nsw i32 %call, %0
35 ; OBJ32-NEXT: Magic: 0x1DF
36 ; OBJ64-NEXT: Magic: 0x1F7
38 ; OBJ-NEXT: TimeStamp: None (0x0)
39 ; OBJ32-NEXT: SymbolTableOffset: 0x13C
40 ; OBJ64-NEXT: SymbolTableOffset: 0x1B8
42 ; OBJ-NEXT: OptionalHeaderSize: 0x0
43 ; OBJ-NEXT: Flags: 0x
[all...]
/llvm-project/libcxxabi/test/vendor/ibm/
H A Daix_xlclang_passing_excp_obj_32.pass.sh.S3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
44 # return 0;
49 .set r0,0; .set SP,1; .set RTOC,2; .set r3,3; .set r4,4
56 .set fp0,0; .set fp1,1; .set fp2,2; .set fp3,3; .set fp4,4
63 .set v0,0; .set v1,1; .set v2,2; .set v3,3; .set v4,4
70 .set x0,0; .set x1,1; .set x2,2; .set x3,3; .set x4,4
83 .set q0,0; .set q1,1; .set q2,2; .set q3,3; .set q4,4
90 .set MQ,0; .set XER,1; .set DSCR,3; .set FROM_RTCU,4; .set FROM_RTCL,5
94 .set BO_dCTR_NZERO_AND_NOT,0; .set BO_dCTR_NZERO_AND_NOT_1,1
105 .set CR0_LT,0;
[all...]
/llvm-project/llvm/test/tools/llvm-readtapi/Inputs/
H A Dmixed-swift-objc.yaml3 magic: 0xFEEDFACF
4 cputype: 0x1000007
5 cpusubtype: 0x3
6 filetype: 0x6
9 flags: 0x110085
10 reserved: 0x0
15 vmaddr: 0
17 fileoff: 0
22 flags: 0
26 addr: 0x1B30
[all …]
/llvm-project/llvm/test/tools/llvm-dwarfdump/X86/Inputs/
H A Dstatistics-fib.s4 .p2align 4, 0x90
9 .loc 1 5 0 # fib.c:5:0
11 # %bb.0: # %entry
27 .loc 1 8 20 is_stmt 0 # fib.c:8:20
49 .loc 1 0 1 is_stmt 0 # fib.c:0:1
56 .loc 1 11 12 is_stmt 0 # fib.c:11:12
85 .p2align 4, 0x90
89 .loc 1 19 0 # fib.c:19:0
91 # %bb.0: # %entry
99 .loc 1 23 7 is_stmt 0 # fib.c:23:7
[all …]
/llvm-project/llvm/test/MC/Disassembler/SystemZ/
H A Dinsns-pcrel.txt6 # 0x00000000:
7 # CHECK: brasl %r0, 0x0
8 0xc0 0x05 0x00 0x00 0x00 0x00
10 # 0x00000006:
11 # CHECK: brasl %r14, 0x
[all...]
/llvm-project/lld/test/wasm/
H A Dmany-functions.ll23 ; CHECK-NEXT: Offset: 0x8
26 ; CHECK-NEXT: Offset: 0x14
29 ; CHECK-NEXT: Offset: 0x20
32 ; CHECK-NEXT: Offset: 0x2C
35 ; CHECK-NEXT: Offset: 0x38
38 ; CHECK-NEXT: Offset: 0x44
41 ; CHECK-NEXT: Offset: 0x50
44 ; CHECK-NEXT: Offset: 0x5C
47 ; CHECK-NEXT: Offset: 0x68
50 ; CHECK-NEXT: Offset: 0x74
[all …]
/llvm-project/lldb/test/API/lang/rust/enum-structs/
H A Dmain.yaml12 AddressAlign: 0x4
16 AddressAlign: 0x10
21 AddressAlign: 0x10
26 AddressAlign: 0x10
31 AddressAlign: 0x10
36 AddressAlign: 0x10
41 AddressAlign: 0x4
46 AddressAlign: 0x10
51 AddressAlign: 0x10
56 AddressAlign: 0x10
[all …]
/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/
H A Dscatter-gather.c11 ….vldr.gather.offset.v8i16.p0.v8i16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 8, i32 0, i32 0)
25 ….vldr.gather.offset.v4i32.p0.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 8, i32 0, i32 0)
39 ….vldr.gather.offset.v16i8.p0.v16i8(ptr [[BASE:%.*]], <16 x i8> [[OFFSET:%.*]], i32 8, i32 0, i32 0)
53 ….vldr.gather.offset.v8i16.p0.v8i16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 8, i32 0, i32 1)
67 ….vldr.gather.offset.v4i32.p0.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 8, i32 0, i32 1)
81 ….vldr.gather.offset.v16i8.p0.v16i8(ptr [[BASE:%.*]], <16 x i8> [[OFFSET:%.*]], i32 8, i32 0, i32 1)
97 …16.p0.v8i16.v8i1(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 8, i32 0, i32 0, <8 x i1> [[TMP1]…
113 …32.p0.v4i32.v4i1(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 8, i32 0, i32 0, <4 x i1> [[TMP1]…
129 …8.p0.v16i8.v16i1(ptr [[BASE:%.*]], <16 x i8> [[OFFSET:%.*]], i32 8, i32 0, i32 0, <16 x i1> [[TMP1…
145 ….v8i16.p0.v8i16.v8i1(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 8, i32 0, i32 1, <8 x i1> [[T…
[all …]
/llvm-project/compiler-rt/test/builtins/Unit/ppc/
H A Dfixunstfti_test.h26 { 0x0p+0, 0x0p+0, INIT_U128( 0x0000000000000000, 0x0000000000000000 ) },
27 { -0x0p+0, 0x0p+0, INIT_U128( 0x0000000000000000, 0x0000000000000000 ) },
28 { -0x0p+0, -0x0p+0, INIT_U128( 0x0000000000000000, 0x0000000000000000 ) },
29 { 0x0p+0, -0x0p+0, INIT_U128( 0x0000000000000000, 0x0000000000000000 ) },
30 { -0x1p+0, 0x0p+0, INIT_U128( 0x0000000000000000, 0x0000000000000000 ) },
31 { 0x1p+0, 0x0p+0, INIT_U128( 0x0000000000000000, 0x0000000000000001 ) },
32 { -INFINITY, 0x0p+0, ((__uint128_t)0x0000000000000000 << 64) | 0x0000000000000000 },
33 { INFINITY, 0x0p+0, ((__uint128_t)0xffffffffffffffff << 64) | 0xffffffffffffffff },
34 { QNAN, 0x0p+0, ((__uint128_t)0x7ff8000000000000 << 64) | 0x0000000000000000 },
35 { -QNAN, 0x0p+0, ((__uint128_t)0x7ff8000000000000 << 64) | 0x0000000000000000 },
[all …]
/llvm-project/llvm/test/CodeGen/X86/
H A Dvector-interleaved-load-i16-stride-3.ll20 ; SSE: # %bb.0:
22 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,3,2,3,4,5,6,7]
23 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,2,2,3]
33 ; AVX: # %bb.0:
35 ; AVX-NEXT: vpshuflw {{.*#+}} xmm1 = xmm0[0,3,2,3,4,5,6,7]
36 ; AVX-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[0,2,2,3]
46 ; AVX2: # %bb.0:
48 ; AVX2-NEXT: vpshuflw {{.*#+}} xmm1 = xmm0[0,3,2,3,4,5,6,7]
49 ; AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[0,2,2,3]
59 ; AVX2-FP: # %bb.0
[all...]
H A Dvector-interleaved-load-i8-stride-8.ll20 ; SSE: # %bb.0:
21 ; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax
22 ; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10
23 ; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r11
25 ; SSE-NEXT: movdqa {{.*#+}} xmm0 = [255,0,0,0,255,0,0,0]
[all...]
H A Dvector-interleaved-load-i32-stride-7.ll20 ; SSE: # %bb.0:
21 ; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax
22 ; SSE-NEXT: movq {{[0-9]+}}(%rsp), %r10
30 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
31 ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
33 ; SSE-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1]
38 ; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm
[all...]
H A Dvector-interleaved-store-i64-stride-6.ll20 ; SSE: # %bb.0:
21 ; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax
29 ; SSE-NEXT: movlhps {{.*#+}} xmm6 = xmm6[0],xmm1[0]
35 ; SSE-NEXT: movlhps {{.*#+}} xmm4 = xmm4[0],xmm5[0]
36 ; SSE-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
46 ; AVX: # %bb.0:
47 ; AVX-NEXT: movq {{[0
[all...]