Lines Matching +full:0 +full:x1b8
11 ….vldr.gather.offset.v8i16.p0.v8i16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 8, i32 0, i32 0)
25 ….vldr.gather.offset.v4i32.p0.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 8, i32 0, i32 0)
39 ….vldr.gather.offset.v16i8.p0.v16i8(ptr [[BASE:%.*]], <16 x i8> [[OFFSET:%.*]], i32 8, i32 0, i32 0)
53 ….vldr.gather.offset.v8i16.p0.v8i16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 8, i32 0, i32 1)
67 ….vldr.gather.offset.v4i32.p0.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 8, i32 0, i32 1)
81 ….vldr.gather.offset.v16i8.p0.v16i8(ptr [[BASE:%.*]], <16 x i8> [[OFFSET:%.*]], i32 8, i32 0, i32 1)
97 …16.p0.v8i16.v8i1(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 8, i32 0, i32 0, <8 x i1> [[TMP1]…
113 …32.p0.v4i32.v4i1(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 8, i32 0, i32 0, <4 x i1> [[TMP1]…
129 …8.p0.v16i8.v16i1(ptr [[BASE:%.*]], <16 x i8> [[OFFSET:%.*]], i32 8, i32 0, i32 0, <16 x i1> [[TMP1…
145 ….v8i16.p0.v8i16.v8i1(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 8, i32 0, i32 1, <8 x i1> [[T…
161 ….v4i32.p0.v4i32.v4i1(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 8, i32 0, i32 1, <4 x i1> [[T…
177 …v16i8.p0.v16i8.v16i1(ptr [[BASE:%.*]], <16 x i8> [[OFFSET:%.*]], i32 8, i32 0, i32 1, <16 x i1> [[…
196 return vldrdq_gather_base_s64(addr, 0x268); in test_vldrdq_gather_base_s64()
206 return vldrdq_gather_base_u64(addr, -0x150); in test_vldrdq_gather_base_u64()
215 // CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP1]], 0
220 return vldrdq_gather_base_wb_s64(addr, 0x240); in test_vldrdq_gather_base_wb_s64()
229 // CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP1]], 0
234 return vldrdq_gather_base_wb_u64(addr, -0x148); in test_vldrdq_gather_base_wb_u64()
245 // CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP3]], 0
250 return vldrdq_gather_base_wb_z_s64(addr, 0x298, p); in test_vldrdq_gather_base_wb_z_s64()
261 // CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP3]], 0
266 return vldrdq_gather_base_wb_z_u64(addr, 0x290, p); in test_vldrdq_gather_base_wb_z_u64()
278 return vldrdq_gather_base_z_s64(addr, 0x378, p); in test_vldrdq_gather_base_z_s64()
290 return vldrdq_gather_base_z_u64(addr, -0x3e8, p); in test_vldrdq_gather_base_z_u64()
295 …vldr.gather.offset.v2i64.p0.v2i64(ptr [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], i32 64, i32 0, i32 0)
309 …vldr.gather.offset.v2i64.p0.v2i64(ptr [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], i32 64, i32 0, i32 1)
325 …4.p0.v2i64.v2i1(ptr [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], i32 64, i32 0, i32 0, <2 x i1> [[TMP1]…
341 …v2i64.p0.v2i64.v2i1(ptr [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], i32 64, i32 0, i32 1, <2 x i1> [[T…
355 …vldr.gather.offset.v2i64.p0.v2i64(ptr [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], i32 64, i32 3, i32 0)
385 ….p0.v2i64.v2i1(ptr [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], i32 64, i32 3, i32 0, <2 x i1> [[TMP1]])
415 …vldr.gather.offset.v8f16.p0.v8i16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 16, i32 0, i32 0)
429 …vldr.gather.offset.v8i16.p0.v8i16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 16, i32 0, i32 0)
443 …vldr.gather.offset.v4i32.p0.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 16, i32 0, i32 0)
457 …vldr.gather.offset.v8i16.p0.v8i16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 16, i32 0, i32 1)
471 …vldr.gather.offset.v4i32.p0.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 16, i32 0, i32 1)
487 …6.p0.v8i16.v8i1(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 16, i32 0, i32 0, <8 x i1> [[TMP1]…
503 …6.p0.v8i16.v8i1(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 16, i32 0, i32 0, <8 x i1> [[TMP1]…
519 …2.p0.v4i32.v4i1(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 16, i32 0, i32 0, <4 x i1> [[TMP1]…
535 …v8i16.p0.v8i16.v8i1(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 16, i32 0, i32 1, <8 x i1> [[T…
551 …v4i32.p0.v4i32.v4i1(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 16, i32 0, i32 1, <4 x i1> [[T…
565 …vldr.gather.offset.v8f16.p0.v8i16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 16, i32 1, i32 0)
579 …vldr.gather.offset.v8i16.p0.v8i16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 16, i32 1, i32 0)
593 …vldr.gather.offset.v4i32.p0.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 16, i32 1, i32 0)
637 ….p0.v8i16.v8i1(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 16, i32 1, i32 0, <8 x i1> [[TMP1]])
653 ….p0.v8i16.v8i1(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], i32 16, i32 1, i32 0, <8 x i1> [[TMP1]])
669 ….p0.v4i32.v4i1(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 16, i32 1, i32 0, <4 x i1> [[TMP1]])
720 return vldrwq_gather_base_f32(addr, 0xc); in test_vldrwq_gather_base_f32()
730 return vldrwq_gather_base_s32(addr, 0x190); in test_vldrwq_gather_base_s32()
740 return vldrwq_gather_base_u32(addr, 0x11c); in test_vldrwq_gather_base_u32()
749 // CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x float>, <4 x i32> } [[TMP1]], 0
754 return vldrwq_gather_base_wb_f32(addr, -0x40); in test_vldrwq_gather_base_wb_f32()
763 // CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[TMP1]], 0
768 return vldrwq_gather_base_wb_s32(addr, 0x50); in test_vldrwq_gather_base_wb_s32()
777 // CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[TMP1]], 0
782 return vldrwq_gather_base_wb_u32(addr, 0x1e0); in test_vldrwq_gather_base_wb_u32()
793 // CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <4 x float>, <4 x i32> } [[TMP3]], 0
798 return vldrwq_gather_base_wb_z_f32(addr, -0x160, p); in test_vldrwq_gather_base_wb_z_f32()
809 // CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[TMP3]], 0
814 return vldrwq_gather_base_wb_z_s32(addr, 0x114, p); in test_vldrwq_gather_base_wb_z_s32()
825 // CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[TMP3]], 0
830 return vldrwq_gather_base_wb_z_u32(addr, 0x58, p); in test_vldrwq_gather_base_wb_z_u32()
842 return vldrwq_gather_base_z_f32(addr, 0x12c, p); in test_vldrwq_gather_base_z_f32()
854 return vldrwq_gather_base_z_s32(addr, 0x1b8, p); in test_vldrwq_gather_base_z_s32()
866 return vldrwq_gather_base_z_u32(addr, -0x12c, p); in test_vldrwq_gather_base_z_u32()
871 …vldr.gather.offset.v4f32.p0.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 32, i32 0, i32 0)
885 …vldr.gather.offset.v4i32.p0.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 32, i32 0, i32 0)
899 …vldr.gather.offset.v4i32.p0.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 32, i32 0, i32 1)
915 …2.p0.v4i32.v4i1(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 32, i32 0, i32 0, <4 x i1> [[TMP1]…
931 …2.p0.v4i32.v4i1(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 32, i32 0, i32 0, <4 x i1> [[TMP1]…
947 …v4i32.p0.v4i32.v4i1(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 32, i32 0, i32 1, <4 x i1> [[T…
961 …vldr.gather.offset.v4f32.p0.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 32, i32 2, i32 0)
975 …vldr.gather.offset.v4i32.p0.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 32, i32 2, i32 0)
1005 ….p0.v4i32.v4i1(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 32, i32 2, i32 0, <4 x i1> [[TMP1]])
1021 ….p0.v4i32.v4i1(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], i32 32, i32 2, i32 0, <4 x i1> [[TMP1]])
1053 …r [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], <8 x i16> [[VALUE:%.*]], i32 8, i32 0, <8 x i1> [[TMP1]])
1069 …r [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x i32> [[VALUE:%.*]], i32 8, i32 0, <4 x i1> [[TMP1]])
1085 … [[BASE:%.*]], <16 x i8> [[OFFSET:%.*]], <16 x i8> [[VALUE:%.*]], i32 8, i32 0, <16 x i1> [[TMP1]])
1101 …r [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], <8 x i16> [[VALUE:%.*]], i32 8, i32 0, <8 x i1> [[TMP1]])
1117 …r [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x i32> [[VALUE:%.*]], i32 8, i32 0, <4 x i1> [[TMP1]])
1133 … [[BASE:%.*]], <16 x i8> [[OFFSET:%.*]], <16 x i8> [[VALUE:%.*]], i32 8, i32 0, <16 x i1> [[TMP1]])
1147 …t.p0.v8i16.v8i16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], <8 x i16> [[VALUE:%.*]], i32 8, i32 0)
1161 …t.p0.v4i32.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x i32> [[VALUE:%.*]], i32 8, i32 0)
1175 …t.p0.v16i8.v16i8(ptr [[BASE:%.*]], <16 x i8> [[OFFSET:%.*]], <16 x i8> [[VALUE:%.*]], i32 8, i32 0)
1189 …t.p0.v8i16.v8i16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], <8 x i16> [[VALUE:%.*]], i32 8, i32 0)
1203 …t.p0.v4i32.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x i32> [[VALUE:%.*]], i32 8, i32 0)
1217 …t.p0.v16i8.v16i8(ptr [[BASE:%.*]], <16 x i8> [[OFFSET:%.*]], <16 x i8> [[VALUE:%.*]], i32 8, i32 0)
1239 vstrdq_scatter_base_p(addr, 0x378, value, p); in test_vstrdq_scatter_base_p_s64()
1241 vstrdq_scatter_base_p_s64(addr, 0x378, value, p); in test_vstrdq_scatter_base_p_s64()
1255 vstrdq_scatter_base_p(addr, 0x108, value, p); in test_vstrdq_scatter_base_p_u64()
1257 vstrdq_scatter_base_p_u64(addr, 0x108, value, p); in test_vstrdq_scatter_base_p_u64()
1269 vstrdq_scatter_base(addr, 0x198, value); in test_vstrdq_scatter_base_s64()
1271 vstrdq_scatter_base_s64(addr, 0x198, value); in test_vstrdq_scatter_base_s64()
1283 vstrdq_scatter_base(addr, -0x1d8, value); in test_vstrdq_scatter_base_u64()
1285 vstrdq_scatter_base_u64(addr, -0x1d8, value); in test_vstrdq_scatter_base_u64()
1301 vstrdq_scatter_base_wb_p(addr, 0xf8, value, p); in test_vstrdq_scatter_base_wb_p_s64()
1303 vstrdq_scatter_base_wb_p_s64(addr, 0xf8, value, p); in test_vstrdq_scatter_base_wb_p_s64()
1319 vstrdq_scatter_base_wb_p(addr, 0x88, value, p); in test_vstrdq_scatter_base_wb_p_u64()
1321 vstrdq_scatter_base_wb_p_u64(addr, 0x88, value, p); in test_vstrdq_scatter_base_wb_p_u64()
1335 vstrdq_scatter_base_wb(addr, 0xd0, value); in test_vstrdq_scatter_base_wb_s64()
1337 vstrdq_scatter_base_wb_s64(addr, 0xd0, value); in test_vstrdq_scatter_base_wb_s64()
1351 vstrdq_scatter_base_wb(addr, -0xa8, value); in test_vstrdq_scatter_base_wb_u64()
1353 vstrdq_scatter_base_wb_u64(addr, -0xa8, value); in test_vstrdq_scatter_base_wb_u64()
1361 … [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], <2 x i64> [[VALUE:%.*]], i32 64, i32 0, <2 x i1> [[TMP1]])
1377 … [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], <2 x i64> [[VALUE:%.*]], i32 64, i32 0, <2 x i1> [[TMP1]])
1391 ….p0.v2i64.v2i64(ptr [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], <2 x i64> [[VALUE:%.*]], i32 64, i32 0)
1405 ….p0.v2i64.v2i64(ptr [[BASE:%.*]], <2 x i64> [[OFFSET:%.*]], <2 x i64> [[VALUE:%.*]], i32 64, i32 0)
1479 …p0.v8i16.v8f16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], <8 x half> [[VALUE:%.*]], i32 16, i32 0)
1495 …[[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], <8 x half> [[VALUE:%.*]], i32 16, i32 0, <8 x i1> [[TMP1]])
1511 … [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], <8 x i16> [[VALUE:%.*]], i32 16, i32 0, <8 x i1> [[TMP1]])
1527 … [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x i32> [[VALUE:%.*]], i32 16, i32 0, <4 x i1> [[TMP1]])
1543 … [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], <8 x i16> [[VALUE:%.*]], i32 16, i32 0, <8 x i1> [[TMP1]])
1559 … [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x i32> [[VALUE:%.*]], i32 16, i32 0, <4 x i1> [[TMP1]])
1573 ….p0.v8i16.v8i16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], <8 x i16> [[VALUE:%.*]], i32 16, i32 0)
1587 ….p0.v4i32.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x i32> [[VALUE:%.*]], i32 16, i32 0)
1601 ….p0.v8i16.v8i16(ptr [[BASE:%.*]], <8 x i16> [[OFFSET:%.*]], <8 x i16> [[VALUE:%.*]], i32 16, i32 0)
1615 ….p0.v4i32.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x i32> [[VALUE:%.*]], i32 16, i32 0)
1785 vstrwq_scatter_base(addr, 0x17c, value); in test_vstrwq_scatter_base_f32()
1787 vstrwq_scatter_base_f32(addr, 0x17c, value); in test_vstrwq_scatter_base_f32()
1801 vstrwq_scatter_base_p(addr, -0x190, value, p); in test_vstrwq_scatter_base_p_f32()
1803 vstrwq_scatter_base_p_f32(addr, -0x190, value, p); in test_vstrwq_scatter_base_p_f32()
1817 vstrwq_scatter_base_p(addr, 0x30, value, p); in test_vstrwq_scatter_base_p_s32()
1819 vstrwq_scatter_base_p_s32(addr, 0x30, value, p); in test_vstrwq_scatter_base_p_s32()
1833 vstrwq_scatter_base_p(addr, -0x178, value, p); in test_vstrwq_scatter_base_p_u32()
1835 vstrwq_scatter_base_p_u32(addr, -0x178, value, p); in test_vstrwq_scatter_base_p_u32()
1847 vstrwq_scatter_base(addr, 0x9c, value); in test_vstrwq_scatter_base_s32()
1849 vstrwq_scatter_base_s32(addr, 0x9c, value); in test_vstrwq_scatter_base_s32()
1861 vstrwq_scatter_base(addr, 0xd4, value); in test_vstrwq_scatter_base_u32()
1863 vstrwq_scatter_base_u32(addr, 0xd4, value); in test_vstrwq_scatter_base_u32()
1877 vstrwq_scatter_base_wb(addr, -0x19c, value); in test_vstrwq_scatter_base_wb_f32()
1879 vstrwq_scatter_base_wb_f32(addr, -0x19c, value); in test_vstrwq_scatter_base_wb_f32()
1895 vstrwq_scatter_base_wb_p(addr, 0xec, value, p); in test_vstrwq_scatter_base_wb_p_f32()
1897 vstrwq_scatter_base_wb_p_f32(addr, 0xec, value, p); in test_vstrwq_scatter_base_wb_p_f32()
1913 vstrwq_scatter_base_wb_p(addr, 0x148, value, p); in test_vstrwq_scatter_base_wb_p_s32()
1915 vstrwq_scatter_base_wb_p_s32(addr, 0x148, value, p); in test_vstrwq_scatter_base_wb_p_s32()
1931 vstrwq_scatter_base_wb_p(addr, 0x19c, value, p); in test_vstrwq_scatter_base_wb_p_u32()
1933 vstrwq_scatter_base_wb_p_u32(addr, 0x19c, value, p); in test_vstrwq_scatter_base_wb_p_u32()
1947 vstrwq_scatter_base_wb(addr, -0x98, value); in test_vstrwq_scatter_base_wb_s32()
1949 vstrwq_scatter_base_wb_s32(addr, -0x98, value); in test_vstrwq_scatter_base_wb_s32()
1963 vstrwq_scatter_base_wb(addr, 0x40, value); in test_vstrwq_scatter_base_wb_u32()
1965 vstrwq_scatter_base_wb_u32(addr, 0x40, value); in test_vstrwq_scatter_base_wb_u32()
1971 …0.v4i32.v4f32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x float> [[VALUE:%.*]], i32 32, i32 0)
1987 …[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x float> [[VALUE:%.*]], i32 32, i32 0, <4 x i1> [[TMP1]])
2003 … [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x i32> [[VALUE:%.*]], i32 32, i32 0, <4 x i1> [[TMP1]])
2019 … [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x i32> [[VALUE:%.*]], i32 32, i32 0, <4 x i1> [[TMP1]])
2033 ….p0.v4i32.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x i32> [[VALUE:%.*]], i32 32, i32 0)
2047 ….p0.v4i32.v4i32(ptr [[BASE:%.*]], <4 x i32> [[OFFSET:%.*]], <4 x i32> [[VALUE:%.*]], i32 32, i32 0)