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/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx10_sopk.txt5 # GFX10: s_addk_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0xff,0xb7]
6 0x34,0x12,0xf
[all...]
H A Dgfx11_dasm_sopk.txt4 # GFX11: s_addk_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0xff,0xb7]
5 0x34,0x12,0xf
[all...]
H A Dgfx12_dasm_sopk.txt4 # GFX12: s_addk_co_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0xff,0xb7]
5 0x34,0x12,0xf
[all...]
H A Dgfx12_dasm_sopp.txt3 # GFX12: s_wait_alu depctr_hold_cnt(0) depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0) ; encoding: [0x00,0x00,0x8
[all...]
H A Dgfx11_dasm_sopp.txt4 # GFX11: s_barrier ; encoding: [0x00,0x00,0xbd,0xbf]
5 0x00,0x00,0xbd,0xbf
7 # GFX11: s_branch 0 ; encoding: [0x0
[all...]
H A Dgfx10_sopp.txt5 # GFX10: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf]
6 0x00,0x00,0x8a,0xbf
8 # GFX10: s_branch 0 ; encoding: [0x0
[all...]
H A Dgfx11_dasm_vopd.txt3 # GFX11: v_dual_add_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x08,0xc9,0x01,0x07,0x06,0xff]
4 0x04,0x0
[all...]
H A Dgfx12_dasm_vopd.txt3 # GFX12: v_dual_add_f32 v255, v4, v2 :: v_dual_add_f32 v6, v1, v3 ; encoding: [0x04,0x05,0x08,0xc9,0x01,0x07,0x06,0xff]
4 0x04,0x0
[all...]
/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx11_asm_sopk.s3 s_movk_i32 s0, 0x1234
4 // GFX11: encoding: [0x34,0x12,0x00,0xb0]
6 s_movk_i32 s0, 0xc1d1
7 // GFX11: encoding: [0xd1,0xc1,0x00,0xb0]
9 s_movk_i32 s105, 0x1234
10 // GFX11: encoding: [0x34,0x12,0x69,0xb0]
12 s_movk_i32 exec_lo, 0x1234
13 // GFX11: encoding: [0x34,0x12,0x7e,0xb0]
15 s_movk_i32 exec_hi, 0x1234
16 // GFX11: encoding: [0x34,0x12,0x7f,0xb0]
[all …]
H A Dgfx12_asm_sopk.s3 s_movk_i32 s0, 0x1234
4 // GFX12: encoding: [0x34,0x12,0x00,0xb0]
6 s_movk_i32 s0, 0xc1d1
7 // GFX12: encoding: [0xd1,0xc1,0x00,0xb0]
9 s_movk_i32 s105, 0x1234
10 // GFX12: encoding: [0x34,0x12,0x69,0xb0]
12 s_movk_i32 exec_lo, 0x1234
13 // GFX12: encoding: [0x34,0x12,0x7e,0xb0]
15 s_movk_i32 exec_hi, 0x1234
16 // GFX12: encoding: [0x34,0x12,0x7f,0xb0]
[all …]
/llvm-project/llvm/test/CodeGen/RISCV/
H A Dmachineoutliner-jumptable.mir8 define i32 @foo(i32 %a, i32 %b) #0 { ret i32 0 }
17 - id: 0
18 blocks: [ '%bb.0', '%bb.1', '%bb.2', '%bb.3' ]
20 bb.0:
24 ; RV32I-MO: $x12 = LUI target-flags(riscv-hi) %jump-table.0
25 ; RV32I-MO: $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0
29 ; RV64I-MO: $x12 = LUI target-flags(riscv-hi) %jump-table.0
30 ; RV64I-MO: $x12 = ADDI $x12, target-flags(riscv-lo) %jump-table.0
33 $x12 = ADDI $x10, 17
34 $x11 = AND $x12, $x11
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dmachine-outliner-drop-stack.mir5 define void @no-save1() #0 { ret void }
6 define void @no-save2() #0 { ret void }
7 define void @reg-save() #0 { ret void }
8 define void @stack-save() #0 { ret void }
9 attributes #0 = { minsize noinline noredzone "frame-pointer"="all" }
16 bb.0:
21 ; CHECK: BL [[FN:@OUTLINED_FUNCTION_[0-9]+]]
25 $x12 = ADDXri $sp, 48, 0;
26 $x12 = ADDXri $sp, 48, 0;
27 $x12 = ADDXri $sp, 48, 0;
[all …]
/llvm-project/llvm/test/MC/X86/
H A DLWP-64.s4 // CHECK: encoding: [0x8f,0xc9,0x78,0x12,0xc5]
8 // CHECK: encoding: [0x8f,0xc9,0xf8,0x12,0xc5]
11 // CHECK: lwpins $0, 485498096, %r15d
12 // CHECK: encoding: [0x8f,0xea,0x00,0x12,0x04,0x25,0xf0,0x1c,0xf0,0x1c,0x00,0x00,0x00,0x00]
13 lwpins $0, 485498096, %r15d
15 // CHECK: lwpins $0, 485498096, %r15
16 // CHECK: encoding: [0x8f,0xea,0x80,0x12,0x04,0x25,0xf0,0x1c,0xf0,0x1c,0x00,0x00,0x00,0x00]
17 lwpins $0, 485498096, %r15
19 // CHECK: lwpins $0, 64(%rdx), %r15d
20 // CHECK: encoding: [0x8f,0xea,0x00,0x12,0x42,0x40,0x00,0x00,0x00,0x00]
[all …]
H A Dlwp-att.s6 # CHECK-X86: encoding: [0x8f,0xe9,0x78,0x12,0xc1]
7 # CHECK-X64: encoding: [0x8f,0xe9,0x78,0x12,0xc1]
11 # CHECK-X86: encoding: [0x8f,0xe9,0x78,0x12,0xc8]
12 # CHECK-X64: encoding: [0x8f,0xe9,0x78,0x12,0xc8]
16 # CHECK-X86: encoding: [0x8f,0xea,0x78,0x12,0xc3,0x78,0x56,0x34,0x12]
17 # CHECK-X64: encoding: [0x8f,0xea,0x78,0x12,0xc3,0x78,0x56,0x34,0x12]
21 # CHECK-X86: encoding: [0x8f,0xea,0x68,0x12,0x04,0x24,0x89,0x67,0x45,0x23]
22 # CHECK-X64: encoding: [0x67,0x8f,0xea,0x68,0x12,0x04,0x24,0x89,0x67,0x45,0x23]
26 # CHECK-X86: encoding: [0x8f,0xea,0x78,0x12,0xcb,0xcd,0xab,0x89,0x67]
27 # CHECK-X64: encoding: [0x8f,0xea,0x78,0x12,0xcb,0xcd,0xab,0x89,0x67]
[all …]
H A DLWP-32.s4 // CHECK: encoding: [0x8f,0xe9,0x78,0x12,0xc0]
7 // CHECK: lwpins $0, -485498096(%edx,%eax,4), %edx
8 // CHECK: encoding: [0x8f,0xea,0x68,0x12,0x84,0x82,0x10,0xe3,0x0f,0xe3,0x00,0x00,0x00,0x00]
9 lwpins $0, -485498096(%edx,%eax,4), %edx
11 // CHECK: lwpins $0, 485498096(%edx,%eax,4), %edx
12 // CHECK: encoding: [0x8f,0xea,0x68,0x12,0x84,0x82,0xf0,0x1c,0xf0,0x1c,0x00,0x00,0x00,0x00]
13 lwpins $0, 485498096(%edx,%eax,4), %edx
15 // CHECK: lwpins $0, 485498096(%edx), %edx
16 // CHECK: encoding: [0x8f,0xea,0x68,0x12,0x82,0xf0,0x1c,0xf0,0x1c,0x00,0x00,0x00,0x00]
17 lwpins $0, 485498096(%edx), %edx
[all …]
/llvm-project/lldb/test/Shell/Register/
H A Dx86-64-ymm-read.test8 # CHECK-DAG: xmm0 = {0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x0
[all...]
H A Dx86-64-ymm-write.test7 …0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x1…
8 …0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x1…
9 …0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x1…
10 …0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x1…
11 …0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x1…
12 …0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x1…
13 …0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x1…
14 …0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1…
15 …0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1…
16 …0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1…
[all …]
H A Dx86-64-write.test13 register write r8 0x0001020304050607
14 register write r9 0x1011121314151617
15 register write r10 0x2021222324252627
16 register write r11 0x3031323334353637
17 register write r12 0x4041424344454647
18 register write r13 0x5051525354555657
19 register write r14 0x6061626364656667
20 register write r15 0x7071727374757677
22 register write xmm8 "{0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x…
23 register write xmm9 "{0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x…
[all …]
/llvm-project/llvm/test/MC/RISCV/
H A Drv32i-aliases-valid.s24 # CHECK-INST: addi a0, zero, 0
25 # CHECK-ALIAS: li a0, 0
26 li x10, 0
60 li x12, 4096
62 li x12, -4096
65 li x12, 4097
68 li x12, -4097
71 li x12, 2147483647
74 li x12, -2147483647
76 li x12,
[all...]
/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/
H A Dselect-rv64.mir11 bb.0:
12 liveins: $x10, $x11, $x12
15 ; CHECK: liveins: $x10, $x11, $x12
17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
19 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
20 …; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, …
23 %0:gprb(s64) = COPY $x10
25 %2:gprb(s64) = COPY $x12
28 %5:gprb(s32) = G_SELECT %0, %3, %4
[all …]
H A Dselect-rv32.mir10 bb.0:
11 liveins: $x10, $x11, $x12
14 ; CHECK: liveins: $x10, $x11, $x12
16 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
17 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
18 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
19 …; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, …
22 %0:gprb(s32) = COPY $x10
24 %2:gprb(s32) = COPY $x12
25 %3:gprb(s32) = G_SELECT %0, %1, %2
[all …]
/llvm-project/llvm/test/MC/AArch64/
H A Dbasic-a64-instructions.s20 add x12, x1, w20, uxtw
26 // CHECK: add x2, x4, w5, uxtb // encoding: [0x82,0x00,0x25,0x8b]
27 // CHECK: add x20, sp, w19, uxth // encoding: [0xf4,0x23,0x33,0x8b]
28 // CHECK: add x12, x
[all...]
/llvm-project/llvm/test/CodeGen/RISCV/rvv/
H A Dzvlsseg-spill.mir16 - { id: 0, offset: 0, size: 64, alignment: 8, stack-id: scalable-vector }
18 bb.0:
26 ; CHECK-NEXT: $x12 = frame-setup PseudoReadVLENB
27 ; CHECK-NEXT: $x12 = frame-setup SLLI killed $x12, 3
28 ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12
29 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0d, 0x7
[all...]
/llvm-project/llvm/test/MC/Mips/
H A Dmul-macro-variants.s14 # CHECK: mul $4, $4, $5 # encoding: [0x70,0x85,0x20,0x02]
15 # CHECK-TRAP: mul $4, $4, $5 # encoding: [0x70,0x85,0x20,0x02]
17 # CHECK: mul $4, $5, $6 # encoding: [0x70,0xa6,0x20,0x02]
18 # CHECK-TRAP: mul $4, $5, $6 # encoding: [0x70,0xa6,0x20,0x02]
19 mul $4, $5, 0
20 # CHECK: addiu $1, $zero, 0 # encoding: [0x24,0x01,0x00,0x00]
21 # CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18]
22 # CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
23 # CHECK-TRAP: addiu $1, $zero, 0 # encoding: [0x24,0x01,0x00,0x00]
24 # CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18]
[all …]
/llvm-project/llvm/test/MC/Disassembler/AArch64/
H A Dbasic-a64-instructions.txt10 # CHECK: add w4, w5, #0
15 0xa4 0x0 0x0 0x11
16 0x62 0xfc 0x3f 0x11
17 0xb
[all...]

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