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Searched defs:pll (Results 1 – 25 of 56) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_dpll_mgr.c63 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_atomic_duplicate_dpll_state() local
111 struct intel_shared_dpll *pll) in intel_get_shared_dpll_id()
122 struct intel_shared_dpll *pll, in assert_shared_dpll()
148 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_prepare_shared_dpll() local
175 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_enable_shared_dpll() local
220 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_disable_shared_dpll() local
260 struct intel_shared_dpll *pll, *unused_pll = NULL; in intel_find_shared_dpll() local
304 const struct intel_shared_dpll *pll, in intel_reference_shared_dpll()
323 const struct intel_shared_dpll *pll) in intel_unreference_shared_dpll()
368 struct intel_shared_dpll *pll = in intel_shared_dpll_swap_state() local
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/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
H A Dnouveau_nvkm_subdev_clk_gk20a.c70 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_read_mnp()
82 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) in gk20a_pllg_write_mnp()
94 gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_calc_rate()
107 struct gk20a_pll *pll) in gk20a_pllg_calc_mnp()
220 struct gk20a_pll pll; in gk20a_pllg_slide() local
301 gk20a_pllg_program_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) in gk20a_pllg_program_mnp()
340 gk20a_pllg_program_mnp_slide(struct gk20a_clk *clk, const struct gk20a_pll *pll) in gk20a_pllg_program_mnp_slide()
470 struct gk20a_pll pll; in gk20a_clk_read() local
555 struct gk20a_pll pll; in gk20a_clk_fini() local
H A Dnouveau_nvkm_subdev_clk_gm20b.c165 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) in gm20b_pllg_read_mnp()
178 gm20b_pllg_write_mnp(struct gm20b_clk *clk, const struct gm20b_pll *pll) in gm20b_pllg_write_mnp()
275 struct gm20b_pll pll; in gm20b_pllg_slide() local
365 gm20b_pllg_program_mnp(struct gm20b_clk *clk, const struct gk20a_pll *pll) in gm20b_pllg_program_mnp()
438 gm20b_pllg_program_mnp_slide(struct gm20b_clk *clk, const struct gk20a_pll *pll) in gm20b_pllg_program_mnp_slide()
493 gm20b_dvfs_calc_safe_pll(struct gm20b_clk *clk, struct gk20a_pll *pll) in gm20b_dvfs_calc_safe_pll()
732 struct gk20a_pll pll; in gm20b_clk_fini() local
H A Dnouveau_nvkm_subdev_clk_gt215.c113 read_pll(struct gt215_clk *clk, int idx, u32 pll) in read_pll()
240 gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz, in gt215_pll_info()
280 int idx, u32 pll, int dom) in calc_clk()
368 prog_pll(struct gt215_clk *clk, int idx, u32 pll, int dom) in prog_pll()
H A Dgt215.h10 u32 pll; member
H A Dgk20a.h121 struct gk20a_pll pll; member
145 gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_n_lo()
/netbsd-src/sys/arch/arm/amlogic/
H A Dmeson_clk_pll.c43 struct meson_clk_pll *pll = &clk->u.pll; in meson_clk_pll_get_rate() local
88 meson_clk_pll_wait_lock(struct meson_clk_softc *sc, struct meson_clk_pll *pll) in meson_clk_pll_wait_lock()
102 struct meson_clk_pll *pll = &clk->u.pll; in meson_clk_pll_set_rate() local
177 struct meson_clk_pll *pll = &clk->u.pll; in meson_clk_pll_get_parent() local
/netbsd-src/sys/arch/arm/nxp/
H A Dimx_ccm_pll.c48 struct imx_ccm_pll *pll = &clk->u.pll; in imx_ccm_pll_enable() local
72 struct imx_ccm_pll *pll= &clk->u.pll; in imx_ccm_pll_get_rate() local
109 struct imx_ccm_pll *pll = &clk->u.pll; in imx_ccm_pll_get_parent() local
H A Dimx6_ccm.c161 struct imx6_clk_pll *pll = &iclk->clk.pll; in imxccm_clk_get_rate_pll_generic() local
177 struct imx6_clk_pll *pll = &iclk->clk.pll; in imxccm_clk_get_rate_pll_sys() local
195 struct imx6_clk_pll *pll = &iclk->clk.pll; imxccm_clk_get_rate_pll_audio_video() local
216 struct imx6_clk_pll *pll = &iclk->clk.pll; imxccm_clk_get_rate_pll_enet() local
242 struct imx6_clk_pll *pll = &iclk->clk.pll; imxccm_clk_get_rate_pll() local
538 struct imx6_clk_pll *pll = &iclk->clk.pll; imxccm_clk_enable_pll() local
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/netbsd-src/sys/dev/i2c/
H A Dtvpll.c47 const struct tvpll_data * pll; member
88 const struct tvpll_data *pll; in tvpll_algo() local
/netbsd-src/sys/arch/arm/rockchip/
H A Drk_cru_pll.c90 struct rk_cru_pll *pll = &clk->u.pll; in rk_cru_pll_get_rate() local
160 struct rk_cru_pll *pll = &clk->u.pll; in rk_cru_pll_set_rate() local
277 struct rk_cru_pll *pll = &clk->u.pll; in rk_cru_pll_get_parent() local
H A Drk3399_pmucru.c164 struct rk_cru_pll *pll = &clk->u.pll; in rk3399_pmucru_pll_get_rate() local
207 struct rk_cru_pll *pll = &clk->u.pll; in rk3399_pmucru_pll_set_rate() local
H A Drk3399_cru.c236 struct rk_cru_pll *pll = &clk->u.pll; in rk3399_cru_pll_get_rate() local
279 struct rk_cru_pll *pll = &clk->u.pll; in rk3399_cru_pll_set_rate() local
/netbsd-src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/qca/
H A Dar9132.dtsi89 pll: pll-controller@18050000 { label
H A Dar9331.dtsi90 pll: pll-controller@18050000 { label
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/sprd/
H A Dsharkl3.dtsi74 pll: pll { label
H A Dsc9860.dtsi195 pll: pll { label
/netbsd-src/sys/arch/mips/atheros/
H A Dar7100.c152 const uint32_t pll = GETPLLREG(ARCHIP_PLL_CPU_PLL_CONFIG); in ar7100_get_freqs() local
H A Dar9344.c124 uint32_t pll; in ar9344_get_freqs() local
/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/
H A Dnouveau_nvkm_subdev_fb_ramnv40.c44 struct nvbios_pll pll; in nv40_ram_calc() local
/netbsd-src/sys/arch/hpcmips/dev/
H A Dmq200subr.c150 mq200_set_pll(struct mq200_softc *sc, int pll, int clock) in mq200_set_pll()
/netbsd-src/sys/arch/x86/include/
H A Dpowernow.h135 unsigned int pll; member
152 uint8_t pll; member
/netbsd-src/sys/arch/arm/samsung/
H A Dexynos_clock.h76 struct exynos_pll_clk pll; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_pll.c121 void amdgpu_pll_compute(struct amdgpu_pll *pll, in amdgpu_pll_compute()
/netbsd-src/sys/arch/arm/nvidia/
H A Dtegra_clock.h82 struct tegra_pll_clk pll; member

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