1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 #ifndef __COMMON_HSI__ 8 #define __COMMON_HSI__ 9 /********************************/ 10 /* PROTOCOL COMMON FW CONSTANTS */ 11 /********************************/ 12 13 /* Temporarily here should be added to HSI automatically by resource allocation 14 * tool. 15 */ 16 #define T_TEST_AGG_INT_TEMP 6 17 #define M_TEST_AGG_INT_TEMP 8 18 #define U_TEST_AGG_INT_TEMP 6 19 #define X_TEST_AGG_INT_TEMP 14 20 #define Y_TEST_AGG_INT_TEMP 4 21 #define P_TEST_AGG_INT_TEMP 4 22 23 #define X_FINAL_CLEANUP_AGG_INT 1 24 25 #define EVENT_RING_PAGE_SIZE_BYTES 4096 26 27 #define NUM_OF_GLOBAL_QUEUES 128 28 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 29 30 #define ISCSI_CDU_TASK_SEG_TYPE 0 31 #define FCOE_CDU_TASK_SEG_TYPE 0 32 #define RDMA_CDU_TASK_SEG_TYPE 1 33 #define ETH_CDU_TASK_SEG_TYPE 2 34 35 #define FW_ASSERT_GENERAL_ATTN_IDX 32 36 37 #define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3 38 39 /* Queue Zone sizes in bytes */ 40 #define TSTORM_QZONE_SIZE 8 /*tstorm_queue_zone*/ 41 /*mstorm_eth_queue_zone. Used only for RX producer of VFs in backward 42 * compatibility mode. 43 */ 44 #define MSTORM_QZONE_SIZE 16 45 #define USTORM_QZONE_SIZE 8 /*ustorm_queue_zone*/ 46 #define XSTORM_QZONE_SIZE 8 /*xstorm_eth_queue_zone*/ 47 #define YSTORM_QZONE_SIZE 0 48 #define PSTORM_QZONE_SIZE 0 49 50 /*Log of mstorm default VF zone size.*/ 51 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 52 /*Maximum number of RX queues that can be allocated to VF by default*/ 53 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 54 /*Maximum number of RX queues that can be allocated to VF with doubled VF zone 55 * size. Up to 96 VF supported in this mode 56 */ 57 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 58 /*Maximum number of RX queues that can be allocated to VF with 4 VF zone size. 59 * Up to 48 VF supported in this mode 60 */ 61 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 62 63 #define ETH_RGSRC_CTX_SIZE 6 /*Size in QREGS*/ 64 #define ETH_TGSRC_CTX_SIZE 6 /*Size in QREGS*/ 65 /********************************/ 66 /* CORE (LIGHT L2) FW CONSTANTS */ 67 /********************************/ 68 69 #define CORE_LL2_MAX_RAMROD_PER_CON 8 70 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 71 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 72 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 73 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 74 75 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 76 77 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 78 79 /* Number of LL2 RAM based (RX producers and statistics) queues */ 80 #define MAX_NUM_LL2_RX_RAM_QUEUES 32 81 /* Number of LL2 context based (RX producers and statistics) queues */ 82 #define MAX_NUM_LL2_RX_CTX_QUEUES 208 83 #define MAX_NUM_LL2_RX_QUEUES (MAX_NUM_LL2_RX_RAM_QUEUES + \ 84 MAX_NUM_LL2_RX_CTX_QUEUES) 85 86 #define MAX_NUM_LL2_TX_STATS_COUNTERS 48 87 88 89 /****************************************************************************/ 90 /* Include firmware version number only- do not add constants here to avoid */ 91 /* redundunt compilations */ 92 /****************************************************************************/ 93 94 95 #define FW_MAJOR_VERSION 8 96 #define FW_MINOR_VERSION 40 97 #define FW_REVISION_VERSION 33 98 #define FW_ENGINEERING_VERSION 0 99 100 /***********************/ 101 /* COMMON HW CONSTANTS */ 102 /***********************/ 103 104 /* PCI functions */ 105 #define MAX_NUM_PORTS_BB (2) 106 #define MAX_NUM_PORTS_K2 (4) 107 #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) 108 109 #define MAX_NUM_PFS_BB (8) 110 #define MAX_NUM_PFS_K2 (16) 111 #define MAX_NUM_PFS (MAX_NUM_PFS_K2) 112 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 113 114 #define MAX_NUM_VFS_BB (120) 115 #define MAX_NUM_VFS_K2 (192) 116 #define COMMON_MAX_NUM_VFS (MAX_NUM_VFS_K2) 117 118 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 119 #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2) 120 121 /* in both BB and K2, the VF number starts from 16. so for arrays containing all 122 * possible PFs and VFs - we need a constant for this size 123 */ 124 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 125 #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2) 126 #define COMMON_MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS_K2) 127 128 #define MAX_NUM_VPORTS_K2 (208) 129 #define MAX_NUM_VPORTS_BB (160) 130 #define COMMON_MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) 131 132 #define MAX_NUM_L2_QUEUES_BB (256) 133 #define MAX_NUM_L2_QUEUES_K2 (320) 134 135 #define FW_LOWEST_CONSUMEDDMAE_CHANNEL (26) 136 137 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 138 #define NUM_PHYS_TCS_4PORT_K2 4 139 #define NUM_OF_PHYS_TCS 8 140 #define PURE_LB_TC NUM_OF_PHYS_TCS 141 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 142 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 143 144 /* CIDs */ 145 #define NUM_OF_CONNECTION_TYPES (8) 146 #define NUM_OF_TASK_TYPES (8) 147 #define NUM_OF_LCIDS (320) 148 #define NUM_OF_LTIDS (320) 149 150 /* Global PXP windows (GTT) */ 151 #define NUM_OF_GTT 19 152 #define GTT_DWORD_SIZE_BITS 10 153 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) 154 #define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS) 155 156 /* Tools Version */ 157 #define TOOLS_VERSION 10 158 /*****************/ 159 /* CDU CONSTANTS */ 160 /*****************/ 161 162 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 163 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 164 165 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 166 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 167 168 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0) 169 #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1) 170 #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2) 171 #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3) 172 #define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4) 173 #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5) 174 175 /*enabled, type A, use all */ 176 #define CDU_CONTEXT_VALIDATION_DEFAULT_CFG (0x3D) 177 178 /*****************/ 179 /* DQ CONSTANTS */ 180 /*****************/ 181 182 /* DEMS */ 183 #define DQ_DEMS_LEGACY 0 184 #define DQ_DEMS_TOE_MORE_TO_SEND 3 185 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4 186 #define DQ_DEMS_ROCE_CQ_CONS 7 187 188 /* XCM agg val selection (HW) */ 189 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 190 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 191 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 192 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 193 #define DQ_XCM_AGG_VAL_SEL_REG3 4 194 #define DQ_XCM_AGG_VAL_SEL_REG4 5 195 #define DQ_XCM_AGG_VAL_SEL_REG5 6 196 #define DQ_XCM_AGG_VAL_SEL_REG6 7 197 198 /* XCM agg val selection (FW) */ 199 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD \ 200 DQ_XCM_AGG_VAL_SEL_WORD2 201 #define DQ_XCM_ETH_TX_BD_CONS_CMD \ 202 DQ_XCM_AGG_VAL_SEL_WORD3 203 #define DQ_XCM_CORE_TX_BD_CONS_CMD \ 204 DQ_XCM_AGG_VAL_SEL_WORD3 205 #define DQ_XCM_ETH_TX_BD_PROD_CMD \ 206 DQ_XCM_AGG_VAL_SEL_WORD4 207 #define DQ_XCM_CORE_TX_BD_PROD_CMD \ 208 DQ_XCM_AGG_VAL_SEL_WORD4 209 #define DQ_XCM_CORE_SPQ_PROD_CMD \ 210 DQ_XCM_AGG_VAL_SEL_WORD4 211 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 212 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 213 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 214 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 215 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 216 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 217 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 218 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 219 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 220 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 221 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 222 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 223 #define DQ_XCM_ROCE_ACK_EDPM_DORQ_SEQ_CMD DQ_XCM_AGG_VAL_SEL_WORD5 224 225 /* UCM agg val selection (HW) */ 226 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 227 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 228 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 229 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 230 #define DQ_UCM_AGG_VAL_SEL_REG0 4 231 #define DQ_UCM_AGG_VAL_SEL_REG1 5 232 #define DQ_UCM_AGG_VAL_SEL_REG2 6 233 #define DQ_UCM_AGG_VAL_SEL_REG3 7 234 235 /* UCM agg val selection (FW) */ 236 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 237 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 238 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 239 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 240 241 /* TCM agg val selection (HW) */ 242 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 243 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 244 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 245 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 246 #define DQ_TCM_AGG_VAL_SEL_REG1 4 247 #define DQ_TCM_AGG_VAL_SEL_REG2 5 248 #define DQ_TCM_AGG_VAL_SEL_REG6 6 249 #define DQ_TCM_AGG_VAL_SEL_REG9 7 250 251 /* TCM agg val selection (FW) */ 252 #define DQ_TCM_L2B_BD_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD1 253 #define DQ_TCM_ROCE_RQ_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD0 254 255 /* XCM agg counter flag selection (HW) */ 256 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 257 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 258 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 259 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 260 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 261 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 262 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 263 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 264 265 /* XCM agg counter flag selection (FW) */ 266 #define DQ_XCM_ETH_DQ_CF_CMD (1 << \ 267 DQ_XCM_AGG_FLG_SHIFT_CF18) 268 #define DQ_XCM_CORE_DQ_CF_CMD (1 << \ 269 DQ_XCM_AGG_FLG_SHIFT_CF18) 270 #define DQ_XCM_ETH_TERMINATE_CMD (1 << \ 271 DQ_XCM_AGG_FLG_SHIFT_CF19) 272 #define DQ_XCM_CORE_TERMINATE_CMD (1 << \ 273 DQ_XCM_AGG_FLG_SHIFT_CF19) 274 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << \ 275 DQ_XCM_AGG_FLG_SHIFT_CF22) 276 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << \ 277 DQ_XCM_AGG_FLG_SHIFT_CF22) 278 #define DQ_XCM_ETH_TPH_EN_CMD (1 << \ 279 DQ_XCM_AGG_FLG_SHIFT_CF23) 280 #define DQ_XCM_FCOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 281 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 282 #define DQ_XCM_ISCSI_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 283 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 284 #define DQ_XCM_TOE_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 285 #define DQ_XCM_TOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 286 287 /* UCM agg counter flag selection (HW) */ 288 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 289 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 290 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 291 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 292 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 293 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 294 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 295 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 296 297 /* UCM agg counter flag selection (FW) */ 298 #define DQ_UCM_NVMF_NEW_CQE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF1) 299 #define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 300 #define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 301 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 302 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 303 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF3) 304 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 305 #define DQ_UCM_TOE_DQ_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 306 307 /* TCM agg counter flag selection (HW) */ 308 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 309 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 310 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 311 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 312 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 313 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 314 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 315 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 316 317 /* TCM agg counter flag selection (FW) */ 318 #define DQ_TCM_FCOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 319 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF2) 320 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 321 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 322 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 323 #define DQ_TCM_TOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 324 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 325 #define DQ_TCM_IWARP_POST_RQ_CF_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 326 327 /* PWM address mapping */ 328 #define DQ_PWM_OFFSET_DPM_BASE 0x0 329 #define DQ_PWM_OFFSET_DPM_END 0x27 330 #define DQ_PWM_OFFSET_XCM32_24ICID_BASE 0x28 331 #define DQ_PWM_OFFSET_UCM32_24ICID_BASE 0x30 332 #define DQ_PWM_OFFSET_TCM32_24ICID_BASE 0x38 333 #define DQ_PWM_OFFSET_XCM16_BASE 0x40 334 #define DQ_PWM_OFFSET_XCM32_BASE 0x44 335 #define DQ_PWM_OFFSET_UCM16_BASE 0x48 336 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C 337 #define DQ_PWM_OFFSET_UCM16_4 0x50 338 #define DQ_PWM_OFFSET_TCM16_BASE 0x58 339 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C 340 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 341 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 342 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 343 344 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 345 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 346 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) 347 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) 348 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 349 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 350 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 351 352 #define DQ_PWM_OFFSET_XCM_RDMA_24B_ICID_SQ_PROD \ 353 (DQ_PWM_OFFSET_XCM32_24ICID_BASE + 2) 354 #define DQ_PWM_OFFSET_UCM_RDMA_24B_ICID_CQ_CONS_32BIT \ 355 (DQ_PWM_OFFSET_UCM32_24ICID_BASE + 4) 356 #define DQ_PWM_OFFSET_TCM_ROCE_24B_ICID_RQ_PROD \ 357 (DQ_PWM_OFFSET_TCM32_24ICID_BASE + 1) 358 359 #define DQ_REGION_SHIFT (12) 360 361 /* DPM */ 362 #define DQ_DPM_WQE_BUFF_SIZE (320) 363 364 /* Conn type ranges */ 365 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 366 367 /*****************/ 368 /* QM CONSTANTS */ 369 /*****************/ 370 371 /* number of TX queues in the QM */ 372 #define MAX_QM_TX_QUEUES_K2 512 373 #define MAX_QM_TX_QUEUES_BB 448 374 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 375 376 /* number of Other queues in the QM */ 377 #define MAX_QM_OTHER_QUEUES_BB 64 378 #define MAX_QM_OTHER_QUEUES_K2 128 379 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 380 381 /* number of queues in a PF queue group */ 382 #define QM_PF_QUEUE_GROUP_SIZE 8 383 384 /* the size of a single queue element in bytes */ 385 #define QM_PQ_ELEMENT_SIZE 4 386 387 /* base number of Tx PQs in the CM PQ representation. 388 * should be used when storing PQ IDs in CM PQ registers and context 389 */ 390 #define CM_TX_PQ_BASE 0x200 391 392 /* number of global Vport/QCN rate limiters */ 393 #define MAX_QM_GLOBAL_RLS 256 394 395 /* number of global rate limiters */ 396 #define MAX_QM_GLOBAL_RLS 256 397 #define COMMON_MAX_QM_GLOBAL_RLS (MAX_QM_GLOBAL_RLS) 398 399 /* QM registers data */ 400 #define QM_LINE_CRD_REG_WIDTH 16 401 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1)) 402 #define QM_BYTE_CRD_REG_WIDTH 24 403 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1)) 404 #define QM_WFQ_CRD_REG_WIDTH 32 405 #define QM_WFQ_CRD_REG_SIGN_BIT (1U << (QM_WFQ_CRD_REG_WIDTH - 1)) 406 #define QM_RL_CRD_REG_WIDTH 32 407 #define QM_RL_CRD_REG_SIGN_BIT (1U << (QM_RL_CRD_REG_WIDTH - 1)) 408 409 /*****************/ 410 /* CAU CONSTANTS */ 411 /*****************/ 412 413 #define CAU_FSM_ETH_RX 0 414 #define CAU_FSM_ETH_TX 1 415 416 /* Number of Protocol Indices per Status Block */ 417 #define PIS_PER_SB 12 418 #define MAX_PIS_PER_SB PIS_PER_SB 419 420 /* fsm is stopped or not valid for this sb */ 421 #define CAU_HC_STOPPED_STATE 3 422 /* fsm is working without interrupt coalescing for this sb*/ 423 #define CAU_HC_DISABLE_STATE 4 424 /* fsm is working with interrupt coalescing for this sb*/ 425 #define CAU_HC_ENABLE_STATE 0 426 427 428 /*****************/ 429 /* IGU CONSTANTS */ 430 /*****************/ 431 432 #define MAX_SB_PER_PATH_K2 (368) 433 #define MAX_SB_PER_PATH_BB (288) 434 #define MAX_TOT_SB_PER_PATH MAX_SB_PER_PATH_K2 435 436 #define MAX_SB_PER_PF_MIMD 129 437 #define MAX_SB_PER_PF_SIMD 64 438 #define MAX_SB_PER_VF 64 439 440 /* Memory addresses on the BAR for the IGU Sub Block */ 441 #define IGU_MEM_BASE 0x0000 442 443 #define IGU_MEM_MSIX_BASE 0x0000 444 #define IGU_MEM_MSIX_UPPER 0x0101 445 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 446 447 #define IGU_MEM_PBA_MSIX_BASE 0x0200 448 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 449 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 450 451 #define IGU_CMD_INT_ACK_BASE 0x0400 452 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 453 454 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 455 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 456 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 457 458 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 459 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 460 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 461 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 462 463 #define IGU_CMD_PROD_UPD_BASE 0x0600 464 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 465 466 /*****************/ 467 /* PXP CONSTANTS */ 468 /*****************/ 469 470 /* Bars for Blocks */ 471 #define PXP_BAR_GRC 0 472 #define PXP_BAR_TSDM 0 473 #define PXP_BAR_USDM 0 474 #define PXP_BAR_XSDM 0 475 #define PXP_BAR_MSDM 0 476 #define PXP_BAR_YSDM 0 477 #define PXP_BAR_PSDM 0 478 #define PXP_BAR_IGU 0 479 #define PXP_BAR_DQ 1 480 481 /* PTT and GTT */ 482 #define PXP_PER_PF_ENTRY_SIZE 8 483 #define PXP_NUM_GLOBAL_WINDOWS 243 484 #define PXP_GLOBAL_ENTRY_SIZE 4 485 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 486 #define PXP_PF_WINDOW_ADMIN_START 0 487 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 488 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \ 489 PXP_PF_WINDOW_ADMIN_LENGTH - 1) 490 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 491 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \ 492 PXP_PER_PF_ENTRY_SIZE) 493 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \ 494 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 495 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 496 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \ 497 PXP_GLOBAL_ENTRY_SIZE) 498 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \ 499 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \ 500 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 501 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 502 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 503 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 504 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 505 506 #define PXP_NUM_PF_WINDOWS 12 507 508 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 509 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 510 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 511 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \ 512 (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \ 513 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 514 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \ 515 (PXP_EXTERNAL_BAR_PF_WINDOW_START + \ 516 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 517 518 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \ 519 (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 520 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 521 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 522 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \ 523 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \ 524 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 525 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \ 526 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \ 527 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 528 529 /* PF BAR */ 530 #define PXP_BAR0_START_GRC 0x0000 531 #define PXP_BAR0_GRC_LENGTH 0x1C00000 532 #define PXP_BAR0_END_GRC \ 533 (PXP_BAR0_START_GRC + PXP_BAR0_GRC_LENGTH - 1) 534 535 #define PXP_BAR0_START_IGU 0x1C00000 536 #define PXP_BAR0_IGU_LENGTH 0x10000 537 #define PXP_BAR0_END_IGU \ 538 (PXP_BAR0_START_IGU + PXP_BAR0_IGU_LENGTH - 1) 539 540 #define PXP_BAR0_START_TSDM 0x1C80000 541 #define PXP_BAR0_SDM_LENGTH 0x40000 542 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 543 #define PXP_BAR0_END_TSDM \ 544 (PXP_BAR0_START_TSDM + PXP_BAR0_SDM_LENGTH - 1) 545 546 #define PXP_BAR0_START_MSDM 0x1D00000 547 #define PXP_BAR0_END_MSDM \ 548 (PXP_BAR0_START_MSDM + PXP_BAR0_SDM_LENGTH - 1) 549 550 #define PXP_BAR0_START_USDM 0x1D80000 551 #define PXP_BAR0_END_USDM \ 552 (PXP_BAR0_START_USDM + PXP_BAR0_SDM_LENGTH - 1) 553 554 #define PXP_BAR0_START_XSDM 0x1E00000 555 #define PXP_BAR0_END_XSDM \ 556 (PXP_BAR0_START_XSDM + PXP_BAR0_SDM_LENGTH - 1) 557 558 #define PXP_BAR0_START_YSDM 0x1E80000 559 #define PXP_BAR0_END_YSDM \ 560 (PXP_BAR0_START_YSDM + PXP_BAR0_SDM_LENGTH - 1) 561 562 #define PXP_BAR0_START_PSDM 0x1F00000 563 #define PXP_BAR0_END_PSDM \ 564 (PXP_BAR0_START_PSDM + PXP_BAR0_SDM_LENGTH - 1) 565 566 #define PXP_BAR0_FIRST_INVALID_ADDRESS \ 567 (PXP_BAR0_END_PSDM + 1) 568 569 /* VF BAR */ 570 #define PXP_VF_BAR0 0 571 572 #define PXP_VF_BAR0_START_IGU 0 573 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 574 #define PXP_VF_BAR0_END_IGU \ 575 (PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1) 576 577 #define PXP_VF_BAR0_START_DQ 0x3000 578 #define PXP_VF_BAR0_DQ_LENGTH 0x200 579 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 580 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS \ 581 (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 582 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS \ 583 (PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4) 584 #define PXP_VF_BAR0_END_DQ \ 585 (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1) 586 587 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 588 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 589 #define PXP_VF_BAR0_END_TSDM_ZONE_B \ 590 (PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 591 592 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 593 #define PXP_VF_BAR0_END_MSDM_ZONE_B \ 594 (PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 595 596 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 597 #define PXP_VF_BAR0_END_USDM_ZONE_B \ 598 (PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 599 600 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 601 #define PXP_VF_BAR0_END_XSDM_ZONE_B \ 602 (PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 603 604 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 605 #define PXP_VF_BAR0_END_YSDM_ZONE_B \ 606 (PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 607 608 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 609 #define PXP_VF_BAR0_END_PSDM_ZONE_B \ 610 (PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 611 612 #define PXP_VF_BAR0_START_GRC 0x3E00 613 #define PXP_VF_BAR0_GRC_LENGTH 0x200 614 #define PXP_VF_BAR0_END_GRC \ 615 (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1) 616 617 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 618 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 619 620 #define PXP_VF_BAR0_START_IGU2 0x10000 621 #define PXP_VF_BAR0_IGU2_LENGTH 0xD000 622 #define PXP_VF_BAR0_END_IGU2 \ 623 (PXP_VF_BAR0_START_IGU2 + PXP_VF_BAR0_IGU2_LENGTH - 1) 624 625 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 626 627 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 628 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 629 630 // ILT Records 631 #define PXP_NUM_ILT_RECORDS_BB 7600 632 #define PXP_NUM_ILT_RECORDS_K2 11000 633 #define MAX_NUM_ILT_RECORDS \ 634 OSAL_MAX_T(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2) 635 636 // Host Interface 637 #define PXP_QUEUES_ZONE_MAX_NUM 320 638 639 640 /*****************/ 641 /* PRM CONSTANTS */ 642 /*****************/ 643 #define PRM_DMA_PAD_BYTES_NUM 2 644 /*****************/ 645 /* SDMs CONSTANTS */ 646 /*****************/ 647 648 649 #define SDM_OP_GEN_TRIG_NONE 0 650 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 651 #define SDM_OP_GEN_TRIG_AGG_INT 2 652 #define SDM_OP_GEN_TRIG_LOADER 4 653 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 654 #define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9 655 656 /***********************************************************/ 657 /* Completion types */ 658 /***********************************************************/ 659 660 #define SDM_COMP_TYPE_NONE 0 661 #define SDM_COMP_TYPE_WAKE_THREAD 1 662 #define SDM_COMP_TYPE_AGG_INT 2 663 /* Send direct message to local CM and/or remote CMs. Destinations are defined 664 * by vector in CompParams. 665 */ 666 #define SDM_COMP_TYPE_CM 3 667 #define SDM_COMP_TYPE_LOADER 4 668 /* Send direct message to PXP (like "internal write" command) to write to remote 669 * Storm RAM via remote SDM 670 */ 671 #define SDM_COMP_TYPE_PXP 5 672 /* Indicate error per thread */ 673 #define SDM_COMP_TYPE_INDICATE_ERROR 6 674 #define SDM_COMP_TYPE_RELEASE_THREAD 7 675 /* Write to local RAM as a completion */ 676 #define SDM_COMP_TYPE_RAM 8 677 #define SDM_COMP_TYPE_INC_ORDER_CNT 9 /* Applicable only for E4 */ 678 679 680 /******************/ 681 /* PBF CONSTANTS */ 682 /******************/ 683 684 /* Number of PBF command queue lines. */ 685 #define PBF_MAX_CMD_LINES 3328 /* Each line is 256b */ 686 687 /* Number of BTB blocks. Each block is 256B. */ 688 #define BTB_MAX_BLOCKS_BB 1440 /* 2880 blocks of 128B */ 689 #define BTB_MAX_BLOCKS_K2 1840 /* 3680 blocks of 128B */ 690 #define BTB_MAX_BLOCKS 1440 691 692 /*****************/ 693 /* PRS CONSTANTS */ 694 /*****************/ 695 696 #define PRS_GFT_CAM_LINES_NO_MATCH 31 697 698 /* 699 * Interrupt coalescing TimeSet 700 */ 701 struct coalescing_timeset { 702 u8 value; 703 /* Interrupt coalescing TimeSet (timeout_ticks = TimeSet shl (TimerRes+1)) */ 704 #define COALESCING_TIMESET_TIMESET_MASK 0x7F 705 #define COALESCING_TIMESET_TIMESET_SHIFT 0 706 /* Only if this flag is set, timeset will take effect */ 707 #define COALESCING_TIMESET_VALID_MASK 0x1 708 #define COALESCING_TIMESET_VALID_SHIFT 7 709 }; 710 711 struct common_queue_zone { 712 __le16 ring_drv_data_consumer; 713 __le16 reserved; 714 }; 715 716 struct nvmf_eqe_data { 717 __le16 icid /* The connection ID for which the EQE is written. */; 718 u8 reserved0[6] /* Alignment to line */; 719 }; 720 721 722 /* 723 * ETH Rx producers data 724 */ 725 struct eth_rx_prod_data { 726 __le16 bd_prod /* BD producer. */; 727 __le16 cqe_prod /* CQE producer. */; 728 }; 729 730 731 struct tcp_ulp_connect_done_params { 732 __le16 mss; 733 u8 snd_wnd_scale; 734 u8 flags; 735 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1 736 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0 737 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F 738 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT 1 739 }; 740 741 struct iscsi_connect_done_results { 742 __le16 icid /* Context ID of the connection */; 743 __le16 conn_id /* Driver connection ID */; 744 /* decided tcp params after connect done */ 745 struct tcp_ulp_connect_done_params params; 746 }; 747 748 749 struct iscsi_eqe_data { 750 __le16 icid /* Context ID of the connection */; 751 __le16 conn_id /* Driver connection ID */; 752 __le16 reserved; 753 /* error code - relevant only if the opcode indicates its an error */ 754 u8 error_code; 755 u8 error_pdu_opcode_reserved; 756 /* The processed PDUs opcode on which happened the error - updated for specific 757 * error codes, by default=0xFF 758 */ 759 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F 760 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 761 /* Indication for driver is the error_pdu_opcode field has valid value */ 762 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 763 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 764 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 765 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 766 }; 767 768 769 /* 770 * Multi function mode 771 */ 772 enum mf_mode { 773 ERROR_MODE /* Unsupported mode */, 774 MF_OVLAN /* Multi function based on outer VLAN */, 775 MF_NPAR /* Multi function based on MAC address (NIC partitioning) */, 776 MAX_MF_MODE 777 }; 778 779 /* Per-protocol connection types */ 780 enum protocol_type { 781 PROTOCOLID_ISCSI /* iSCSI */, 782 PROTOCOLID_FCOE /* FCoE */, 783 PROTOCOLID_ROCE /* RoCE */, 784 PROTOCOLID_CORE /* Core (light L2, slow path core) */, 785 PROTOCOLID_ETH /* Ethernet */, 786 PROTOCOLID_IWARP /* iWARP */, 787 PROTOCOLID_TOE /* TOE */, 788 PROTOCOLID_PREROCE /* Pre (tapeout) RoCE */, 789 PROTOCOLID_COMMON /* ProtocolCommon */, 790 PROTOCOLID_TCP /* TCP */, 791 PROTOCOLID_RDMA /* RDMA */, 792 PROTOCOLID_SCSI /* SCSI */, 793 MAX_PROTOCOL_TYPE 794 }; 795 796 797 struct regpair { 798 __le32 lo /* low word for reg-pair */; 799 __le32 hi /* high word for reg-pair */; 800 }; 801 802 /* 803 * RoCE Destroy Event Data 804 */ 805 struct rdma_eqe_destroy_qp { 806 __le32 cid /* Dedicated field RoCE destroy QP event */; 807 u8 reserved[4]; 808 }; 809 810 /* 811 * RoCE Suspend Event Data 812 */ 813 struct rdma_eqe_suspend_qp { 814 __le32 cid /* Dedicated field RoCE Suspend QP event */; 815 u8 reserved[4]; 816 }; 817 818 /* 819 * RDMA Event Data Union 820 */ 821 union rdma_eqe_data { 822 struct regpair async_handle /* Host handle for the Async Completions */; 823 /* RoCE Destroy Event Data */ 824 struct rdma_eqe_destroy_qp rdma_destroy_qp_data; 825 /* RoCE Suspend QP Event Data */ 826 struct rdma_eqe_suspend_qp rdma_suspend_qp_data; 827 }; 828 829 struct tstorm_queue_zone { 830 __le32 reserved[2]; 831 }; 832 833 834 /* 835 * Ustorm Queue Zone 836 */ 837 struct ustorm_eth_queue_zone { 838 /* Rx interrupt coalescing TimeSet */ 839 struct coalescing_timeset int_coalescing_timeset; 840 u8 reserved[3]; 841 }; 842 843 844 struct ustorm_queue_zone { 845 struct ustorm_eth_queue_zone eth; 846 struct common_queue_zone common; 847 }; 848 849 /* status block structure */ 850 struct cau_pi_entry { 851 __le32 prod; 852 /* A per protocol indexPROD value. */ 853 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF 854 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 855 /* This value determines the TimeSet that the PI is associated with */ 856 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F 857 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 858 /* Select the FSM within the SB */ 859 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 860 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 861 /* Select the FSM within the SB */ 862 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF 863 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 864 }; 865 866 /* status block structure */ 867 struct cau_sb_entry { 868 __le32 data; 869 /* The SB PROD index which is sent to the IGU. */ 870 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF 871 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 872 #define CAU_SB_ENTRY_STATE0_MASK 0xF /* RX state */ 873 #define CAU_SB_ENTRY_STATE0_SHIFT 24 874 #define CAU_SB_ENTRY_STATE1_MASK 0xF /* TX state */ 875 #define CAU_SB_ENTRY_STATE1_SHIFT 28 876 __le32 params; 877 /* Indicates the RX TimeSet that this SB is associated with. */ 878 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F 879 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 880 /* Indicates the TX TimeSet that this SB is associated with. */ 881 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F 882 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 883 /* This value will determine the RX FSM timer resolution in ticks */ 884 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 885 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 886 /* This value will determine the TX FSM timer resolution in ticks */ 887 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 888 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 889 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 890 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 891 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 892 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 893 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 894 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 895 /* If set then indicates that the TPH STAG is equal to the SB number. Otherwise 896 * the STAG will be equal to all ones. 897 */ 898 #define CAU_SB_ENTRY_TPH_MASK 0x1 899 #define CAU_SB_ENTRY_TPH_SHIFT 31 900 }; 901 902 903 /* 904 * Igu cleanup bit values to distinguish between clean or producer consumer 905 * update. 906 */ 907 enum command_type_bit { 908 IGU_COMMAND_TYPE_NOP = 0, 909 IGU_COMMAND_TYPE_SET = 1, 910 MAX_COMMAND_TYPE_BIT 911 }; 912 913 914 /* core doorbell data */ 915 struct core_db_data { 916 u8 params; 917 /* destination of doorbell (use enum db_dest) */ 918 #define CORE_DB_DATA_DEST_MASK 0x3 919 #define CORE_DB_DATA_DEST_SHIFT 0 920 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 921 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 922 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 923 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 924 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 925 #define CORE_DB_DATA_RESERVED_MASK 0x1 926 #define CORE_DB_DATA_RESERVED_SHIFT 5 927 /* aggregative value selection */ 928 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 929 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 930 /* bit for every DQ counter flags in CM context that DQ can increment */ 931 u8 agg_flags; 932 __le16 spq_prod; 933 }; 934 935 /* Enum of doorbell aggregative command selection */ 936 enum db_agg_cmd_sel { 937 DB_AGG_CMD_NOP /* No operation */, 938 DB_AGG_CMD_SET /* Set the value */, 939 DB_AGG_CMD_ADD /* Add the value */, 940 DB_AGG_CMD_MAX /* Set max of current and new value */, 941 MAX_DB_AGG_CMD_SEL 942 }; 943 944 /* Enum of doorbell destination */ 945 enum db_dest { 946 DB_DEST_XCM /* TX doorbell to XCM */, 947 DB_DEST_UCM /* RX doorbell to UCM */, 948 DB_DEST_TCM /* RX doorbell to TCM */, 949 DB_NUM_DESTINATIONS, 950 MAX_DB_DEST 951 }; 952 953 954 /* 955 * Enum of doorbell DPM types 956 */ 957 enum db_dpm_type { 958 DPM_LEGACY /* Legacy DPM- to Xstorm RAM */, 959 DPM_RDMA /* RDMA DPM (only RoCE in E4) - to NIG */, 960 /* L2 DPM inline- to PBF, with packet data on doorbell */ 961 DPM_L2_INLINE, 962 DPM_L2_BD /* L2 DPM with BD- to PBF, with TX BD data on doorbell */, 963 MAX_DB_DPM_TYPE 964 }; 965 966 /* 967 * Structure for doorbell data, in L2 DPM mode, for the first doorbell in a DPM 968 * burst 969 */ 970 struct db_l2_dpm_data { 971 __le16 icid /* internal CID */; 972 __le16 bd_prod /* bd producer value to update */; 973 __le32 params; 974 /* Size in QWORD-s of the DPM burst */ 975 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F 976 #define DB_L2_DPM_DATA_SIZE_SHIFT 0 977 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type) 978 */ 979 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 980 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 981 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */ 982 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 983 /* size of the packet to be transmitted in bytes */ 984 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF 985 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 986 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 987 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 988 /* In DPM_L2_BD mode: the number of SGE-s */ 989 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 990 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 991 /* Flag indicating whether to enable GFS search */ 992 #define DB_L2_DPM_DATA_RESERVED1_MASK 0x1 993 #define DB_L2_DPM_DATA_RESERVED1_SHIFT 31 994 }; 995 996 /* 997 * Structure for SGE in a DPM doorbell of type DPM_L2_BD 998 */ 999 struct db_l2_dpm_sge { 1000 struct regpair addr /* Single continuous buffer */; 1001 __le16 nbytes /* Number of bytes in this BD. */; 1002 __le16 bitfields; 1003 /* The TPH STAG index value */ 1004 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF 1005 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 1006 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 1007 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 1008 /* Indicate if ST hint is requested or not */ 1009 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 1010 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 1011 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 1012 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 1013 __le32 reserved2; 1014 }; 1015 1016 /* Structure for doorbell address, in legacy mode */ 1017 struct db_legacy_addr { 1018 __le32 addr; 1019 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 1020 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 1021 /* doorbell extraction mode specifier- 0 if not used */ 1022 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 1023 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 1024 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF /* internal CID */ 1025 #define DB_LEGACY_ADDR_ICID_SHIFT 5 1026 }; 1027 1028 /* 1029 * Structure for doorbell address, in PWM mode 1030 */ 1031 struct db_pwm_addr { 1032 __le32 addr; 1033 #define DB_PWM_ADDR_RESERVED0_MASK 0x7 1034 #define DB_PWM_ADDR_RESERVED0_SHIFT 0 1035 /* Offset in PWM address space */ 1036 #define DB_PWM_ADDR_OFFSET_MASK 0x7F 1037 #define DB_PWM_ADDR_OFFSET_SHIFT 3 1038 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */ 1039 #define DB_PWM_ADDR_WID_SHIFT 10 1040 #define DB_PWM_ADDR_DPI_MASK 0xFFFF /* Doorbell page ID */ 1041 #define DB_PWM_ADDR_DPI_SHIFT 12 1042 #define DB_PWM_ADDR_RESERVED1_MASK 0xF 1043 #define DB_PWM_ADDR_RESERVED1_SHIFT 28 1044 }; 1045 1046 /* 1047 * Structure for doorbell address, in legacy mode, without DEMS 1048 */ 1049 struct db_legacy_wo_dems_addr { 1050 __le32 addr; 1051 #define DB_LEGACY_WO_DEMS_ADDR_RESERVED0_MASK 0x3 1052 #define DB_LEGACY_WO_DEMS_ADDR_RESERVED0_SHIFT 0 1053 #define DB_LEGACY_WO_DEMS_ADDR_ICID_MASK 0x3FFFFFFF /* internal CID */ 1054 #define DB_LEGACY_WO_DEMS_ADDR_ICID_SHIFT 2 1055 }; 1056 1057 1058 /* 1059 * Parameters to RDMA firmware, passed in EDPM doorbell 1060 */ 1061 struct db_rdma_dpm_params { 1062 __le32 params; 1063 /* Size in QWORD-s of the DPM burst */ 1064 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F 1065 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 1066 /* Type of DPM transacation (DPM_RDMA) (use enum db_dpm_type) */ 1067 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 1068 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 1069 /* opcode for RDMA operation */ 1070 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF 1071 #define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 1072 /* the size of the WQE payload in bytes */ 1073 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF 1074 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 1075 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 1076 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 1077 /* RoCE ack request (will be set 1) */ 1078 #define DB_RDMA_DPM_PARAMS_ACK_REQUEST_MASK 0x1 1079 #define DB_RDMA_DPM_PARAMS_ACK_REQUEST_SHIFT 28 1080 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */ 1081 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 1082 /* RoCE completion flag for FW use */ 1083 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 1084 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 30 1085 /* Connection type is iWARP */ 1086 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 1087 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 1088 }; 1089 1090 /* 1091 * Parameters to RDMA firmware, passed in EDPM doorbell 1092 */ 1093 struct db_rdma_24b_icid_dpm_params { 1094 __le32 params; 1095 /* Size in QWORD-s of the DPM burst */ 1096 #define DB_RDMA_24B_ICID_DPM_PARAMS_SIZE_MASK 0x3F 1097 #define DB_RDMA_24B_ICID_DPM_PARAMS_SIZE_SHIFT 0 1098 /* Type of DPM transacation (DPM_RDMA) (use enum db_dpm_type) */ 1099 #define DB_RDMA_24B_ICID_DPM_PARAMS_DPM_TYPE_MASK 0x3 1100 #define DB_RDMA_24B_ICID_DPM_PARAMS_DPM_TYPE_SHIFT 6 1101 /* opcode for RDMA operation */ 1102 #define DB_RDMA_24B_ICID_DPM_PARAMS_OPCODE_MASK 0xFF 1103 #define DB_RDMA_24B_ICID_DPM_PARAMS_OPCODE_SHIFT 8 1104 /* ICID extension */ 1105 #define DB_RDMA_24B_ICID_DPM_PARAMS_ICID_EXT_MASK 0xFF 1106 #define DB_RDMA_24B_ICID_DPM_PARAMS_ICID_EXT_SHIFT 16 1107 /* Number of invalid bytes in last QWROD of the DPM transaction */ 1108 #define DB_RDMA_24B_ICID_DPM_PARAMS_INV_BYTE_CNT_MASK 0x7 1109 #define DB_RDMA_24B_ICID_DPM_PARAMS_INV_BYTE_CNT_SHIFT 24 1110 /* Flag indicating 24b icid mode is enabled */ 1111 #define DB_RDMA_24B_ICID_DPM_PARAMS_EXT_ICID_MODE_EN_MASK 0x1 1112 #define DB_RDMA_24B_ICID_DPM_PARAMS_EXT_ICID_MODE_EN_SHIFT 27 1113 /* RoCE completion flag */ 1114 #define DB_RDMA_24B_ICID_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 1115 #define DB_RDMA_24B_ICID_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 1116 /* RoCE S flag */ 1117 #define DB_RDMA_24B_ICID_DPM_PARAMS_S_FLG_MASK 0x1 1118 #define DB_RDMA_24B_ICID_DPM_PARAMS_S_FLG_SHIFT 29 1119 #define DB_RDMA_24B_ICID_DPM_PARAMS_RESERVED1_MASK 0x1 1120 #define DB_RDMA_24B_ICID_DPM_PARAMS_RESERVED1_SHIFT 30 1121 /* Connection type is iWARP */ 1122 #define DB_RDMA_24B_ICID_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 1123 #define DB_RDMA_24B_ICID_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 1124 }; 1125 1126 1127 /* 1128 * Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a 1129 * DPM burst 1130 */ 1131 struct db_rdma_dpm_data { 1132 __le16 icid /* internal CID */; 1133 __le16 prod_val /* aggregated value to update */; 1134 /* parameters passed to RDMA firmware */ 1135 struct db_rdma_dpm_params params; 1136 }; 1137 1138 /* Igu interrupt command */ 1139 enum igu_int_cmd { 1140 IGU_INT_ENABLE = 0, 1141 IGU_INT_DISABLE = 1, 1142 IGU_INT_NOP = 2, 1143 IGU_INT_NOP2 = 3, 1144 MAX_IGU_INT_CMD 1145 }; 1146 1147 /* IGU producer or consumer update command */ 1148 struct igu_prod_cons_update { 1149 __le32 sb_id_and_flags; 1150 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 1151 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 1152 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 1153 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 1154 /* interrupt enable/disable/nop (use enum igu_int_cmd) */ 1155 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 1156 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 1157 /* (use enum igu_seg_access) */ 1158 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 1159 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 1160 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 1161 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 1162 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 1163 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 1164 /* must always be set cleared (use enum command_type_bit) */ 1165 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 1166 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 1167 __le32 reserved1; 1168 }; 1169 1170 /* Igu segments access for default status block only */ 1171 enum igu_seg_access { 1172 IGU_SEG_ACCESS_REG = 0, 1173 IGU_SEG_ACCESS_ATTN = 1, 1174 MAX_IGU_SEG_ACCESS 1175 }; 1176 1177 1178 /* 1179 * Enumeration for L3 type field of parsing_and_err_flags_union. L3Type: 1180 * 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according 1181 * to the last-ethertype) 1182 */ 1183 enum l3_type { 1184 e_l3_type_unknown, 1185 e_l3_type_ipv4, 1186 e_l3_type_ipv6, 1187 MAX_L3_TYPE 1188 }; 1189 1190 1191 /* 1192 * Enumeration for l4Protocol field of parsing_and_err_flags_union. L4-protocol 1193 * 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the 1194 * first fragment, the protocol-type should be set to none. 1195 */ 1196 enum l4_protocol { 1197 e_l4_protocol_none, 1198 e_l4_protocol_tcp, 1199 e_l4_protocol_udp, 1200 MAX_L4_PROTOCOL 1201 }; 1202 1203 1204 /* 1205 * Parsing and error flags field. 1206 */ 1207 struct parsing_and_err_flags { 1208 __le16 flags; 1209 /* L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled 1210 * according to the last-ethertype) (use enum l3_type) 1211 */ 1212 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 1213 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 1214 /* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and 1215 * its not the first fragment, the protocol-type should be set to none. 1216 * (use enum l4_protocol) 1217 */ 1218 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 1219 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 1220 /* Set if the packet is IPv4 fragment. */ 1221 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 1222 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 1223 /* Set if VLAN tag exists. Invalid if tunnel type are IP GRE or IP GENEVE. */ 1224 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 1225 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 1226 /* Set if L4 checksum was calculated. */ 1227 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 1228 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 1229 /* Set for PTP packet. */ 1230 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 1231 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 1232 /* Set if PTP timestamp recorded. */ 1233 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 1234 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 1235 /* Set if either version-mismatch or hdr-len-error or ipv4-cksm is set or ipv6 1236 * ver mismatch 1237 */ 1238 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 1239 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 1240 /* Set if L4 checksum validation failed. Valid only if L4 checksum was 1241 * calculated. 1242 */ 1243 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 1244 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 1245 /* Set if GRE/VXLAN/GENEVE tunnel detected. */ 1246 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 1247 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 1248 /* Set if VLAN tag exists in tunnel header. */ 1249 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 1250 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 1251 /* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or 1252 * tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch 1253 */ 1254 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 1255 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 1256 /* Set if GRE or VXLAN/GENEVE UDP checksum was calculated. */ 1257 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 1258 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1259 /* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum 1260 * was calculated. 1261 */ 1262 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 1263 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1264 }; 1265 1266 1267 /* 1268 * Parsing error flags bitmap. 1269 */ 1270 struct parsing_err_flags { 1271 __le16 flags; 1272 /* MAC error indication */ 1273 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1 1274 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0 1275 /* truncation error indication */ 1276 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1 1277 #define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1 1278 /* packet too small indication */ 1279 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1 1280 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2 1281 /* Header Missing Tag */ 1282 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1 1283 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3 1284 /* from frame cracker output */ 1285 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1 1286 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4 1287 /* from frame cracker output */ 1288 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1 1289 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5 1290 /* set this error if: 1. total-len is smaller than hdr-len 2. total-ip-len 1291 * indicates number that is bigger than real packet length 3. tunneling: 1292 * total-ip-length of the outer header points to offset that is smaller than 1293 * the one pointed to by the total-ip-len of the inner hdr. 1294 */ 1295 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1 1296 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6 1297 /* from frame cracker output */ 1298 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1 1299 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7 1300 /* from frame cracker output. for either TCP or UDP */ 1301 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1 1302 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8 1303 /* from frame cracker output */ 1304 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1 1305 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9 1306 /* cksm calculated and value isn't 0xffff or L4-cksm-wasnt-calculated for any 1307 * reason, like: udp/ipv4 checksum is 0 etc. 1308 */ 1309 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1 1310 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10 1311 /* from frame cracker output */ 1312 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1 1313 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11 1314 /* from frame cracker output */ 1315 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1 1316 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12 1317 /* set if geneve option size was over 32 byte */ 1318 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1 1319 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13 1320 /* from frame cracker output */ 1321 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1 1322 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14 1323 /* from frame cracker output */ 1324 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1 1325 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15 1326 }; 1327 1328 1329 /* 1330 * Pb context 1331 */ 1332 struct pb_context { 1333 __le32 crc[4]; 1334 }; 1335 1336 /* Concrete Function ID. */ 1337 struct pxp_concrete_fid { 1338 __le16 fid; 1339 #define PXP_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1340 #define PXP_CONCRETE_FID_PFID_SHIFT 0 1341 #define PXP_CONCRETE_FID_PORT_MASK 0x3 /* port number */ 1342 #define PXP_CONCRETE_FID_PORT_SHIFT 4 1343 #define PXP_CONCRETE_FID_PATH_MASK 0x1 /* path number */ 1344 #define PXP_CONCRETE_FID_PATH_SHIFT 6 1345 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1346 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1347 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 1348 #define PXP_CONCRETE_FID_VFID_SHIFT 8 1349 }; 1350 1351 struct pxp_pretend_concrete_fid { 1352 __le16 fid; 1353 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF 1354 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1355 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 1356 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1357 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1358 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1359 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1360 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1361 }; 1362 1363 union pxp_pretend_fid { 1364 struct pxp_pretend_concrete_fid concrete_fid; 1365 __le16 opaque_fid; 1366 }; 1367 1368 /* Pxp Pretend Command Register. */ 1369 struct pxp_pretend_cmd { 1370 union pxp_pretend_fid fid; 1371 __le16 control; 1372 #define PXP_PRETEND_CMD_PATH_MASK 0x1 1373 #define PXP_PRETEND_CMD_PATH_SHIFT 0 1374 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1375 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1376 #define PXP_PRETEND_CMD_PORT_MASK 0x3 1377 #define PXP_PRETEND_CMD_PORT_SHIFT 2 1378 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1379 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1380 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1381 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1382 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 1383 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1384 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 1385 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1386 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 1387 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1388 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 1389 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1390 }; 1391 1392 /* PTT Record in PXP Admin Window. */ 1393 struct pxp_ptt_entry { 1394 __le32 offset; 1395 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1396 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1397 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1398 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1399 struct pxp_pretend_cmd pretend; 1400 }; 1401 1402 1403 /* 1404 * VF Zone A Permission Register. 1405 */ 1406 struct pxp_vf_zone_a_permission { 1407 __le32 control; 1408 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1409 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1410 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1411 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1412 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1413 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1414 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1415 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1416 }; 1417 1418 1419 /* 1420 * Rdif context 1421 */ 1422 struct rdif_task_context { 1423 __le32 initial_ref_tag; 1424 __le16 app_tag_value; 1425 __le16 app_tag_mask; 1426 u8 flags0; 1427 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1428 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1429 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1430 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1431 /* 0 = IP checksum, 1 = CRC */ 1432 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 1433 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1434 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1435 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1436 /* 1/2/3 - Protection Type */ 1437 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 1438 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1439 /* 0=0x0000, 1=0xffff */ 1440 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1441 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1442 /* Keep reference tag constant */ 1443 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 1444 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7 1445 u8 partial_dif_data[7]; 1446 __le16 partial_crc_value; 1447 __le16 partial_checksum_value; 1448 __le32 offset_in_io; 1449 __le16 flags1; 1450 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1451 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1452 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1453 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1454 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1455 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1456 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1457 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1458 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1459 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1460 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1461 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1462 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1463 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 1464 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1465 /* 0=None, 1=DIF, 2=DIX */ 1466 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 1467 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1468 /* DIF tag right at the beginning of DIF interval */ 1469 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 1470 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1471 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1472 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1473 /* 0=None, 1=DIF */ 1474 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 1475 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1476 /* Forward application tag with mask */ 1477 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 1478 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14 1479 /* Forward reference tag with mask */ 1480 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 1481 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15 1482 __le16 state; 1483 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF 1484 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0 1485 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF 1486 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4 1487 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1 1488 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8 1489 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1 1490 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9 1491 /* mask for refernce tag handling */ 1492 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF 1493 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10 1494 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1495 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1496 __le32 reserved2; 1497 }; 1498 1499 /* 1500 * RSS hash type 1501 */ 1502 enum rss_hash_type { 1503 RSS_HASH_TYPE_DEFAULT = 0, 1504 RSS_HASH_TYPE_IPV4 = 1, 1505 RSS_HASH_TYPE_TCP_IPV4 = 2, 1506 RSS_HASH_TYPE_IPV6 = 3, 1507 RSS_HASH_TYPE_TCP_IPV6 = 4, 1508 RSS_HASH_TYPE_UDP_IPV4 = 5, 1509 RSS_HASH_TYPE_UDP_IPV6 = 6, 1510 MAX_RSS_HASH_TYPE 1511 }; 1512 1513 /* 1514 * status block structure 1515 */ 1516 struct status_block { 1517 __le16 pi_array[PIS_PER_SB]; 1518 __le32 sb_num; 1519 #define STATUS_BLOCK_SB_NUM_MASK 0x1FF 1520 #define STATUS_BLOCK_SB_NUM_SHIFT 0 1521 #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F 1522 #define STATUS_BLOCK_ZERO_PAD_SHIFT 9 1523 #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF 1524 #define STATUS_BLOCK_ZERO_PAD2_SHIFT 16 1525 __le32 prod_index; 1526 #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF 1527 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0 1528 #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF 1529 #define STATUS_BLOCK_ZERO_PAD3_SHIFT 24 1530 }; 1531 1532 1533 /* 1534 * Tdif context 1535 */ 1536 struct tdif_task_context { 1537 __le32 initial_ref_tag; 1538 __le16 app_tag_value; 1539 __le16 app_tag_mask; 1540 __le16 partial_crc_value_b; 1541 __le16 partial_checksum_value_b; 1542 __le16 stateB; 1543 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF 1544 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0 1545 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF 1546 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4 1547 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1 1548 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8 1549 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1 1550 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9 1551 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1552 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1553 u8 reserved1; 1554 u8 flags0; 1555 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1556 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1557 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1558 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1559 /* 0 = IP checksum, 1 = CRC */ 1560 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 1561 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1562 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1563 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1564 /* 1/2/3 - Protection Type */ 1565 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 1566 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1567 /* 0=0x0000, 1=0xffff */ 1568 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1569 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1570 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1571 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1572 __le32 flags1; 1573 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1574 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1575 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1576 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1577 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1578 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1579 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1580 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1581 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1582 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1583 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1584 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1585 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1586 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 1587 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1588 /* 0=None, 1=DIF, 2=DIX */ 1589 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 1590 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1591 /* DIF tag right at the beginning of DIF interval */ 1592 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 1593 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1594 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 /* reserved */ 1595 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1596 /* 0=None, 1=DIF */ 1597 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 1598 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1599 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF 1600 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14 1601 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF 1602 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18 1603 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1 1604 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22 1605 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1 1606 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23 1607 /* mask for refernce tag handling */ 1608 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF 1609 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24 1610 /* Forward application tag with mask */ 1611 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 1612 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28 1613 /* Forward reference tag with mask */ 1614 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 1615 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29 1616 /* Keep reference tag constant */ 1617 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 1618 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30 1619 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1620 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1621 __le32 offset_in_io_b; 1622 __le16 partial_crc_value_a; 1623 __le16 partial_checksum_value_a; 1624 __le32 offset_in_io_a; 1625 u8 partial_dif_data_a[8]; 1626 u8 partial_dif_data_b[8]; 1627 }; 1628 1629 1630 /* 1631 * Timers context 1632 */ 1633 struct timers_context { 1634 __le32 logical_client_0; 1635 /* Expiration time of logical client 0 */ 1636 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF 1637 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 1638 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1 1639 #define TIMERS_CONTEXT_RESERVED0_SHIFT 27 1640 /* Valid bit of logical client 0 */ 1641 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 1642 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 1643 /* Active bit of logical client 0 */ 1644 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 1645 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 1646 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 1647 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 1648 __le32 logical_client_1; 1649 /* Expiration time of logical client 1 */ 1650 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF 1651 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 1652 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1 1653 #define TIMERS_CONTEXT_RESERVED2_SHIFT 27 1654 /* Valid bit of logical client 1 */ 1655 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 1656 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 1657 /* Active bit of logical client 1 */ 1658 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 1659 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 1660 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3 1661 #define TIMERS_CONTEXT_RESERVED3_SHIFT 30 1662 __le32 logical_client_2; 1663 /* Expiration time of logical client 2 */ 1664 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF 1665 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 1666 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1 1667 #define TIMERS_CONTEXT_RESERVED4_SHIFT 27 1668 /* Valid bit of logical client 2 */ 1669 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 1670 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 1671 /* Active bit of logical client 2 */ 1672 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 1673 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 1674 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3 1675 #define TIMERS_CONTEXT_RESERVED5_SHIFT 30 1676 __le32 host_expiration_fields; 1677 /* Expiration time on host (closest one) */ 1678 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF 1679 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 1680 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1 1681 #define TIMERS_CONTEXT_RESERVED6_SHIFT 27 1682 /* Valid bit of host expiration */ 1683 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 1684 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 1685 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7 1686 #define TIMERS_CONTEXT_RESERVED7_SHIFT 29 1687 }; 1688 1689 1690 /* 1691 * Enum for next_protocol field of tunnel_parsing_flags 1692 */ 1693 enum tunnel_next_protocol { 1694 e_unknown = 0, 1695 e_l2 = 1, 1696 e_ipv4 = 2, 1697 e_ipv6 = 3, 1698 MAX_TUNNEL_NEXT_PROTOCOL 1699 }; 1700 1701 #endif /* __COMMON_HSI__ */ 1702